445             regs->ctrl_regs.reg9.fbc_e = 1;  in set_registers()
449             regs->ctrl_regs.reg9.tile_e = 1;  in set_registers()
453             regs->ctrl_regs.reg9.fbc_e = 0;  in set_registers()
571 …         vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);  in set_registers()
575 …         vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);  in set_registers()
579             regs->ctrl_regs.reg9.scale_down_en = 0;  in set_registers()
589     Vdpu383CtrlReg *ctrl_regs = &regs->ctrl_regs;  in init_ctrl_regs()  local
591     ctrl_regs->reg8_dec_mode = 1;  //!< h264  in init_ctrl_regs()
592     ctrl_regs->reg9.buf_empty_en = 0;  in init_ctrl_regs()
594     ctrl_regs->reg10.strmd_auto_gating_e      = 1;  in init_ctrl_regs()
595     ctrl_regs->reg10.inter_auto_gating_e      = 1;  in init_ctrl_regs()
596     ctrl_regs->reg10.intra_auto_gating_e      = 1;  in init_ctrl_regs()
597     ctrl_regs->reg10.transd_auto_gating_e     = 1;  in init_ctrl_regs()
598     ctrl_regs->reg10.recon_auto_gating_e      = 1;  in init_ctrl_regs()
599     ctrl_regs->reg10.filterd_auto_gating_e    = 1;  in init_ctrl_regs()
600     ctrl_regs->reg10.bus_auto_gating_e        = 1;  in init_ctrl_regs()
601     ctrl_regs->reg10.ctrl_auto_gating_e       = 1;  in init_ctrl_regs()
602     ctrl_regs->reg10.rcb_auto_gating_e        = 1;  in init_ctrl_regs()
603     ctrl_regs->reg10.err_prc_auto_gating_e    = 1;  in init_ctrl_regs()
605     ctrl_regs->reg13_core_timeout_threshold = 0xffffff;  in init_ctrl_regs()
607     ctrl_regs->reg16.error_proc_disable = 1;  in init_ctrl_regs()
608     ctrl_regs->reg16.error_spread_disable = 0;  in init_ctrl_regs()
609     ctrl_regs->reg16.roi_error_ctu_cal_en = 0;  in init_ctrl_regs()
611     ctrl_regs->reg20_cabac_error_en_lowbits = 0xfffedfff;  in init_ctrl_regs()
612     ctrl_regs->reg21_cabac_error_en_highbits = 0x0ffbf9ff;  in init_ctrl_regs()
615     ctrl_regs->reg28.axi_perf_work_e = 1;  in init_ctrl_regs()
616     ctrl_regs->reg28.axi_cnt_type = 1;  in init_ctrl_regs()
617     ctrl_regs->reg28.rd_latency_id = 11;  in init_ctrl_regs()
619     ctrl_regs->reg29.addr_align_type = 2;  in init_ctrl_regs()
620     ctrl_regs->reg29.ar_cnt_id_type = 0;  in init_ctrl_regs()
621     ctrl_regs->reg29.aw_cnt_id_type = 0;  in init_ctrl_regs()
622     ctrl_regs->reg29.ar_count_id = 0xa;  in init_ctrl_regs()
623     ctrl_regs->reg29.aw_count_id = 0;  in init_ctrl_regs()
624     ctrl_regs->reg29.rd_band_width_mode = 0;  in init_ctrl_regs()
914     vdpu383_setup_statistic(&regs->ctrl_regs);  in vdpu383_h264d_gen_regs()
942         wr_cfg.reg = &regs->ctrl_regs;  in vdpu383_h264d_start()
943         wr_cfg.size = sizeof(regs->ctrl_regs);  in vdpu383_h264d_start()
978         rd_cfg.reg = &regs->ctrl_regs.reg15;  in vdpu383_h264d_start()
979         rd_cfg.size = sizeof(regs->ctrl_regs.reg15);  in vdpu383_h264d_start()
1029         if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||  in vdpu383_h264d_wait()
1030             p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||  in vdpu383_h264d_wait()
1031             p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||  in vdpu383_h264d_wait()
1032             p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||  in vdpu383_h264d_wait()
1033             p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||  in vdpu383_h264d_wait()
1034             p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||  in vdpu383_h264d_wait()
1035             p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)  in vdpu383_h264d_wait()
1042     memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32));  in vdpu383_h264d_wait()