861             vp9_hw_regs->ctrl_regs.reg9.fbc_e = 1;  in hal_vp9d_vdpu383_gen_regs()
873             vp9_hw_regs->ctrl_regs.reg9.fbc_e = 0;  in hal_vp9d_vdpu383_gen_regs()
875                 vp9_hw_regs->ctrl_regs.reg9.tile_e = 1;  in hal_vp9d_vdpu383_gen_regs()
879                 vp9_hw_regs->ctrl_regs.reg9.tile_e = 0;  in hal_vp9d_vdpu383_gen_regs()
1020     vp9_hw_regs->ctrl_regs.reg8_dec_mode = 2; //set as vp9 dec  in hal_vp9d_vdpu383_gen_regs()
1021     vp9_hw_regs->ctrl_regs.reg9.buf_empty_en = 0;  in hal_vp9d_vdpu383_gen_regs()
1023     vp9_hw_regs->ctrl_regs.reg10.strmd_auto_gating_e      = 1;  in hal_vp9d_vdpu383_gen_regs()
1024     vp9_hw_regs->ctrl_regs.reg10.inter_auto_gating_e      = 1;  in hal_vp9d_vdpu383_gen_regs()
1025     vp9_hw_regs->ctrl_regs.reg10.intra_auto_gating_e      = 1;  in hal_vp9d_vdpu383_gen_regs()
1026     vp9_hw_regs->ctrl_regs.reg10.transd_auto_gating_e     = 1;  in hal_vp9d_vdpu383_gen_regs()
1027     vp9_hw_regs->ctrl_regs.reg10.recon_auto_gating_e      = 1;  in hal_vp9d_vdpu383_gen_regs()
1028     vp9_hw_regs->ctrl_regs.reg10.filterd_auto_gating_e    = 1;  in hal_vp9d_vdpu383_gen_regs()
1029     vp9_hw_regs->ctrl_regs.reg10.bus_auto_gating_e        = 1;  in hal_vp9d_vdpu383_gen_regs()
1030     vp9_hw_regs->ctrl_regs.reg10.ctrl_auto_gating_e       = 1;  in hal_vp9d_vdpu383_gen_regs()
1031     vp9_hw_regs->ctrl_regs.reg10.rcb_auto_gating_e        = 1;  in hal_vp9d_vdpu383_gen_regs()
1032     vp9_hw_regs->ctrl_regs.reg10.err_prc_auto_gating_e    = 1;  in hal_vp9d_vdpu383_gen_regs()
1034     vp9_hw_regs->ctrl_regs.reg16.error_proc_disable = 1;  in hal_vp9d_vdpu383_gen_regs()
1035     vp9_hw_regs->ctrl_regs.reg16.error_spread_disable = 0;  in hal_vp9d_vdpu383_gen_regs()
1036     vp9_hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0;  in hal_vp9d_vdpu383_gen_regs()
1038     vp9_hw_regs->ctrl_regs.reg20_cabac_error_en_lowbits = 0xffffffdf;  in hal_vp9d_vdpu383_gen_regs()
1039     vp9_hw_regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3fffffff;  in hal_vp9d_vdpu383_gen_regs()
1041     vp9_hw_regs->ctrl_regs.reg13_core_timeout_threshold = 0x3ffff;  in hal_vp9d_vdpu383_gen_regs()
1084     vdpu383_setup_statistic(&vp9_hw_regs->ctrl_regs);  in hal_vp9d_vdpu383_gen_regs()
1110             vdpu383_setup_down_scale(mframe, p_hal->dev, &vp9_hw_regs->ctrl_regs,  in hal_vp9d_vdpu383_gen_regs()
1115             vdpu383_setup_down_scale(mframe, p_hal->dev, &vp9_hw_regs->ctrl_regs,  in hal_vp9d_vdpu383_gen_regs()
1120             vp9_hw_regs->ctrl_regs.reg9.scale_down_en = 0;  in hal_vp9d_vdpu383_gen_regs()
1148         wr_cfg.reg = &hw_regs->ctrl_regs;  in hal_vp9d_vdpu383_start()
1149         wr_cfg.size = sizeof(hw_regs->ctrl_regs);  in hal_vp9d_vdpu383_start()
1184         rd_cfg.reg = &hw_regs->ctrl_regs.reg15;  in hal_vp9d_vdpu383_start()
1185         rd_cfg.size = sizeof(hw_regs->ctrl_regs.reg15);  in hal_vp9d_vdpu383_start()
1270         (!hw_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||  in hal_vp9d_vdpu383_wait()
1271         hw_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||  in hal_vp9d_vdpu383_wait()
1272         hw_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||  in hal_vp9d_vdpu383_wait()
1273         hw_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||  in hal_vp9d_vdpu383_wait()
1274         hw_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||  in hal_vp9d_vdpu383_wait()
1275         hw_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||  in hal_vp9d_vdpu383_wait()
1276         hw_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) {  in hal_vp9d_vdpu383_wait()