381             regs->ctrl_regs.reg9.dpb_data_sel = 0;  in set_registers()
382             regs->ctrl_regs.reg9.dpb_output_dis = 0;  in set_registers()
383             regs->ctrl_regs.reg9.pp_m_output_mode = 0;  in set_registers()
389             regs->ctrl_regs.reg9.dpb_data_sel = 1;  in set_registers()
390             regs->ctrl_regs.reg9.dpb_output_dis = 1;  in set_registers()
391             regs->ctrl_regs.reg9.pp_m_output_mode = 2;  in set_registers()
397             regs->ctrl_regs.reg9.dpb_data_sel = 1;  in set_registers()
398             regs->ctrl_regs.reg9.dpb_output_dis = 1;  in set_registers()
399             regs->ctrl_regs.reg9.pp_m_output_mode = 1;  in set_registers()
526 …        vdpu384a_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);  in set_registers()
530 …        vdpu384a_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);  in set_registers()
534             regs->ctrl_regs.reg9.scale_down_en = 0;  in set_registers()
544     Vdpu384aCtrlReg *ctrl_regs = &regs->ctrl_regs;  in init_ctrl_regs()  local
546     ctrl_regs->reg8_dec_mode = 1;  //!< h264  in init_ctrl_regs()
547     ctrl_regs->reg9.low_latency_en = 0;  in init_ctrl_regs()
549     ctrl_regs->reg10.strmd_auto_gating_e      = 1;  in init_ctrl_regs()
550     ctrl_regs->reg10.inter_auto_gating_e      = 1;  in init_ctrl_regs()
551     ctrl_regs->reg10.intra_auto_gating_e      = 1;  in init_ctrl_regs()
552     ctrl_regs->reg10.transd_auto_gating_e     = 1;  in init_ctrl_regs()
553     ctrl_regs->reg10.recon_auto_gating_e      = 1;  in init_ctrl_regs()
554     ctrl_regs->reg10.filterd_auto_gating_e    = 1;  in init_ctrl_regs()
555     ctrl_regs->reg10.bus_auto_gating_e        = 1;  in init_ctrl_regs()
556     ctrl_regs->reg10.ctrl_auto_gating_e       = 1;  in init_ctrl_regs()
557     ctrl_regs->reg10.rcb_auto_gating_e        = 1;  in init_ctrl_regs()
558     ctrl_regs->reg10.err_prc_auto_gating_e    = 1;  in init_ctrl_regs()
560     ctrl_regs->reg11.rd_outstanding = 32;  in init_ctrl_regs()
561     ctrl_regs->reg11.wr_outstanding = 250;  in init_ctrl_regs()
563     ctrl_regs->reg13_core_timeout_threshold = 0xffffff;  in init_ctrl_regs()
565     ctrl_regs->reg16.error_proc_disable = 1;  in init_ctrl_regs()
566     ctrl_regs->reg16.error_spread_disable = 0;  in init_ctrl_regs()
567     ctrl_regs->reg16.roi_error_ctu_cal_en = 0;  in init_ctrl_regs()
569     ctrl_regs->reg20_cabac_error_en_lowbits = 0xfffedfff;  in init_ctrl_regs()
570     ctrl_regs->reg21_cabac_error_en_highbits = 0x0ffbf9ff;  in init_ctrl_regs()
573     ctrl_regs->reg28.axi_perf_work_e = 1;  in init_ctrl_regs()
574     ctrl_regs->reg28.axi_cnt_type = 1;  in init_ctrl_regs()
575     ctrl_regs->reg28.rd_latency_id = 11;  in init_ctrl_regs()
577     ctrl_regs->reg29.addr_align_type = 2;  in init_ctrl_regs()
578     ctrl_regs->reg29.ar_cnt_id_type = 0;  in init_ctrl_regs()
579     ctrl_regs->reg29.aw_cnt_id_type = 0;  in init_ctrl_regs()
580     ctrl_regs->reg29.ar_count_id = 0xa;  in init_ctrl_regs()
581     ctrl_regs->reg29.aw_count_id = 0;  in init_ctrl_regs()
582     ctrl_regs->reg29.rd_band_width_mode = 0;  in init_ctrl_regs()
860     vdpu384a_setup_statistic(&regs->ctrl_regs);  in vdpu384a_h264d_gen_regs()
888         wr_cfg.reg = &regs->ctrl_regs;  in vdpu384a_h264d_start()
889         wr_cfg.size = sizeof(regs->ctrl_regs);  in vdpu384a_h264d_start()
924         rd_cfg.reg = &regs->ctrl_regs.reg15;  in vdpu384a_h264d_start()
925         rd_cfg.size = sizeof(regs->ctrl_regs.reg15);  in vdpu384a_h264d_start()
975         if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||  in vdpu384a_h264d_wait()
976             p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||  in vdpu384a_h264d_wait()
977             p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||  in vdpu384a_h264d_wait()
978             p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||  in vdpu384a_h264d_wait()
979             p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||  in vdpu384a_h264d_wait()
980             p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||  in vdpu384a_h264d_wait()
981             p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)  in vdpu384a_h264d_wait()
988     memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32));  in vdpu384a_h264d_wait()