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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dstart.S71 adr x0, _start /* x0 <- Runtime value of _start */
73 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
82 add x0, x0, x9
84 str x4, [x0]
98 adr x0, vectors
100 3: msr vbar_el3, x0
101 mrs x0, scr_el3
102 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
103 msr scr_el3, x0
[all …]
H A Dcache.S27 lsl x12, x0, #1
73 mov x1, x0
80 mov x0, #0 /* start flush at cache level 0 */
87 lsl x12, x0, #1
88 add x12, x12, x0 /* x0 <- tripled cache level */
95 add x0, x0, #1 /* increment cache level */
96 cmp x11, x0
99 mov x0, #0
100 msr csselr_el1, x0 /* restore csselr_el1 */
112 mov x0, #0
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dfsl-ls1046a.dtsi30 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
31 <0x0 0x1420000 0 0x10000>, /* GICC */
32 <0x0 0x1440000 0 0x20000>, /* GICH */
33 <0x0 0x1460000 0 0x20000>; /* GICV */
45 reg = <0x0 0x1ee1000 0x0 0x1000>;
54 reg = <0x0 0x2100000 0x0 0x10000>;
67 reg = <0x0 0x2110000 0x0 0x10000>;
78 reg = <0x0 0x1530000 0x0 0x10000>;
86 reg = <0x0 0x2180000 0x0 0x10000>;
97 reg = <0x0 0x2190000 0x0 0x10000>;
[all …]
H A Dfsl-ls1043a.dtsi30 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
31 <0x0 0x1402000 0 0x2000>, /* GICC */
32 <0x0 0x1404000 0 0x2000>, /* GICH */
33 <0x0 0x1406000 0 0x2000>; /* GICV */
45 reg = <0x0 0x1ee1000 0x0 0x1000>;
54 reg = <0x0 0x2100000 0x0 0x10000>;
67 reg = <0x0 0x2110000 0x0 0x10000>;
78 reg = <0x0 0x1530000 0x0 0x10000>;
86 reg = <0x0 0x2180000 0x0 0x10000>;
97 reg = <0x0 0x2190000 0x0 0x10000>;
[all …]
H A Dfsl-ls2080a.dtsi23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
41 reg = <0x0 0x21c0500 0x0 0x100>;
49 reg = <0x0 0x21c0600 0x0 0x100>;
64 reg = <0x0 0x2100000 0x0 0x10000>;
73 reg = <0x0 0x20c0000 0x0 0x10000>,
74 <0x0 0x20000000 0x0 0x10000000>;
81 reg = <0x0 0x3100000 0x0 0x10000>;
88 reg = <0x0 0x3110000 0x0 0x10000>;
95 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
[all …]
H A Dfsl-ls1012a.dtsi24 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
25 <0x0 0x1402000 0 0x2000>, /* GICC */
26 <0x0 0x1404000 0 0x2000>, /* GICH */
27 <0x0 0x1406000 0 0x2000>; /* GICV */
39 reg = <0x0 0x1ee1000 0x0 0x1000>;
48 reg = <0x0 0x2100000 0x0 0x10000>;
59 reg = <0x0 0x1560000 0x0 0x10000>;
67 reg = <0x0 0x1580000 0x0 0x10000>;
78 reg = <0x0 0x2180000 0x0 0x10000>;
89 reg = <0x0 0x2190000 0x0 0x10000>;
[all …]
H A Dtegra210.dtsi17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
82 reg = <0x0 0x50000000 0x0 0x00034000>;
93 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
[all …]
H A Dmeson-gx.dtsi65 reg = <0x0 0x0 0x0 0x1000000>;
71 reg = <0x0 0x10000000 0x0 0x200000>;
78 size = <0x0 0xbc00000>;
79 alignment = <0x0 0x400000>;
86 #size-cells = <0x0>;
91 reg = <0x0 0x0>;
100 reg = <0x0 0x1>;
109 reg = <0x0 0x2>;
118 reg = <0x0 0x3>;
216 reg = <0x0 0xc1100000 0x0 0x100000>;
[all …]
H A Dzynqmp.dtsi24 reg = <0x0>;
76 #power-domain-cells = <0x0>;
81 #power-domain-cells = <0x0>;
86 #power-domain-cells = <0x0>;
91 #power-domain-cells = <0x0>;
96 #power-domain-cells = <0x0>;
101 #power-domain-cells = <0x0>;
106 #power-domain-cells = <0x0>;
111 #power-domain-cells = <0x0>;
116 #power-domain-cells = <0x0>;
[all …]
H A Dtegra186.dtsi19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
76 reg = <0x0 0x3180000 0x0 0x100>;
89 reg = <0x0 0x3190000 0x0 0x100>;
102 reg = <0x0 0x31b0000 0x0 0x100>;
115 reg = <0x0 0x31c0000 0x0 0x100>;
128 reg = <0x0 0x31e0000 0x0 0x100>;
[all …]
H A Dthunderx-88xx.dtsi28 reg = <0x0 0x000>;
34 reg = <0x0 0x001>;
40 reg = <0x0 0x002>;
46 reg = <0x0 0x003>;
52 reg = <0x0 0x004>;
58 reg = <0x0 0x005>;
64 reg = <0x0 0x006>;
70 reg = <0x0 0x007>;
76 reg = <0x0 0x008>;
82 reg = <0x0 0x009>;
[all …]
H A Dhi6220.dtsi59 reg = <0x0 0x0>;
66 reg = <0x0 0x1>;
73 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
87 reg = <0x0 0x100>;
94 reg = <0x0 0x101>;
101 reg = <0x0 0x102>;
108 reg = <0x0 0x103>;
115 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
116 <0x0 0xf6802000 0 0x2000>, /* GICC */
[all …]
H A Drk3588.dtsi31 reg = <0x0 0xfc400000 0x0 0x400000>;
50 reg = <0x0 0xfd5b8000 0x0 0x10000>;
55 reg = <0x0 0xfd5c0000 0x0 0x100>;
60 reg = <0x0 0xfd5cc000 0x0 0x4000>;
66 reg = <0x0 0xfd5d4000 0x0 0x4000>;
90 reg = <0x0 0xfd5e4000 0x0 0x100>;
95 reg = <0x0 0xfddb8000 0x0 0x1000>;
107 reg = <0x0 0xfddc8000 0x0 0x1000>;
121 reg = <0x0 0xfdde8000 0x0 0x1000>;
133 reg = <0x0 0xfddf4000 0x0 0x1000>;
[all …]
H A Drk3568.dtsi63 reg = <0x0 0x0>;
72 reg = <0x0 0x100>;
81 reg = <0x0 0x200>;
90 reg = <0x0 0x300>;
267 reg = <0x0 0xfcc00000 0x0 0x400000>;
299 reg = <0x0 0xfd000000 0x0 0x400000>;
326 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
327 <0x0 0xfd460000 0 0xc0000>; /* GICR */
332 reg = <0x0 0xfd440000 0x0 0x20000>;
339 reg = <0x0 0xfd800000 0x0 0x40000>;
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/armada8k/
H A Dcache_llc.S19 mov x0, #LLC_BASE_ADDR
20 add x0, x0, #LLC_FLUSH_BY_WAY
21 movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
23 str w1, [x0]
25 mov x0, #LLC_BASE_ADDR
26 add x0, x0, #LLC_CACHE_SYNC
27 movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
28 str wzr, [x0]
30 mov x0, #LLC_BASE_ADDR
31 add x0, x0, #LLC_CACHE_SYNC_COMPLETE
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S32 ldr x0, =GICD_BASE
51 ldr x0, =GICD_BASE_64K
82 ldr x0, =CCI_AUX_CONTROL_BASE(20)
98 ldr x0, =CCI_AUX_CONTROL_BASE(6)
101 ldr x0, =CCI_AUX_CONTROL_BASE(20)
108 ldr x0, =CCI_MN_BASE
114 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
117 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
120 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
124 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
[all …]
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dsetjmp_aarch64.S14 stp x19, x20, [x0,#0]
15 stp x21, x22, [x0,#16]
16 stp x23, x24, [x0,#32]
17 stp x25, x26, [x0,#48]
18 stp x27, x28, [x0,#64]
19 stp x29, x30, [x0,#80]
21 str x2, [x0, #96]
22 mov x0, #0
29 ldp x19, x20, [x0,#0]
30 ldp x21, x22, [x0,#16]
[all …]
H A Dcrt0_64.S74 ldr x0, =(CONFIG_TPL_STACK)
76 ldr x0, =(CONFIG_SPL_STACK)
78 ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
80 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
81 mov x0, sp
83 mov sp, x0
85 mov x18, x0
98 ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */
99 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
106 adr x0, _start /* x0 <- Runtime value of _start */
[all …]
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/acpi/
H A Dsleepstates.asl7 Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
8 Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
9 Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
10 Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-baytrail/acpi/
H A Dsleepstates.asl10 Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
12 Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
14 Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
15 Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
/rk3399_rockchip-uboot/drivers/rknand/
H A Drk_zftl_arm_v8.S24 ldrb w5, [x0, x3]
80 ldr x1, [x0]
87 mov x22, x0
95 adrp x0, .LC0
98 add x0, x0, :lo12:.LC0
101 ldr x0, [x22]
103 cmp x19, x0
123 ldr x0, [x21, #:lo12:.LANCHOR4]
125 umaddl x3, w3, w1, x0
138 umull x0, w0, w1
[all …]
H A Drk_zftl_spl_arm_v8.S24 ldrb w5, [x0, x3]
80 ldr x1, [x0]
87 mov x22, x0
95 adrp x0, .LC0
98 add x0, x0, :lo12:.LC0
101 ldr x0, [x22]
103 cmp x19, x0
123 ldr x0, [x21, #:lo12:.LANCHOR4]
125 umaddl x3, w3, w1, x0
138 umull x0, w0, w1
[all …]
H A Drk_ftl_arm_v8.S16 ubfiz x0, x0, 4, 8
20 add x2, x1, x0
22 ldr x0, [x1, x0]
25 add x19, x0, x19, lsl 8
28 mov x0, 80
54 ubfx x1, x0, 5, 11
73 ldrb w4, [x0, 1]
87 ldrb w5, [x0, x3]
149 adrp x0, .LANCHOR5
150 add x0, x0, :lo12:.LANCHOR5
[all …]
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dcrownbay.dts72 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
73 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
74 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
81 reg = <0x0000b800 0x0 0x0 0x0 0x0>;
88 reg = <0x00010000 0x0 0x0 0x0 0x0>;
97 reg = <0x00025100 0x0 0x0 0x0 0x0
98 0x01025110 0x0 0x0 0x0 0x0>;
111 reg = <0x00025200 0x0 0x0 0x0 0x0
112 0x01025210 0x0 0x0 0x0 0x0>;
125 reg = <0x00025300 0x0 0x0 0x0 0x0
[all …]
/rk3399_rockchip-uboot/drivers/rkflash/
H A Drk_sftl_arm_v8.S82 adrp x0, .LANCHOR7
83 ldr w0, [x0, #:lo12:.LANCHOR7]
85 adrp x0, .LANCHOR6
86 str w1, [x0, #:lo12:.LANCHOR6]
96 mov x5, x0
100 ldrh w3, [x0]
101 adrp x0, .LANCHOR8
104 strh w3, [x0, #:lo12:.LANCHOR8]
105 adrp x0, .LANCHOR9
107 strh w4, [x0, #:lo12:.LANCHOR9]
[all …]

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