arm: cache v8: Add isb sync before __asm_flush_dcache_range() out

Promising flush operation is really done before a DMA start. The
issue was found on eMMC read with RK3588 A76 big core boot.

The sa

arm: cache v8: Add isb sync before __asm_flush_dcache_range() out

Promising flush operation is really done before a DMA start. The
issue was found on eMMC read with RK3588 A76 big core boot.

The same reason as commit:
(1d85e75e20 arm: cache v8: add isb sync for clean/invalidate)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide34f474f8d49f04869cb832a4b382b3c4b31fff

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arm: cache v8: add isb sync for clean/invalidate

When rk3588 boot with big core on U-Boot and enter rockusb
download mode, it works abnormally.

We find that a isb() is neccessary before cache inval

arm: cache v8: add isb sync for clean/invalidate

When rk3588 boot with big core on U-Boot and enter rockusb
download mode, it works abnormally.

We find that a isb() is neccessary before cache invalidate.
We guess that the A76's prefetch performance is too powerful.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I4492a073f4d38b337f177d3d3970ec2c9107d5df

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

armv8: move low-level assembly functions into function-sections

TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option

armv8: move low-level assembly functions into function-sections

TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway. By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.

Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.

Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Support cache invalidate

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operat

arm: Support cache invalidate

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-tegra

armv8: add hooks for all cache-wide operations

SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 po

armv8: add hooks for all cache-wide operations

SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

arm64: rename __asm_flush_dcache_level to __asm_dcache_level

Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cach

arm64: rename __asm_flush_dcache_level to __asm_dcache_level

Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: fix comment "flush & invalidate"

We should say "clean & invalidate", or simply "flush".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm64: optimize __asm_{flush, invalidate}_dcache_all

__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.

We do not have to waste x16 register here.

Signed-of

arm64: optimize __asm_{flush, invalidate}_dcache_all

__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.

We do not have to waste x16 register here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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arm64: Make full va map code more dynamic

The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k

arm64: Make full va map code more dynamic

The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf <agraf@suse.de>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-arm

arm: armv8 correct value passed to __asm_dcache_all

>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"

Current value 0xffff can make invalidate work, since we only judge whet

arm: armv8 correct value passed to __asm_dcache_all

>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"

Current value 0xffff can make invalidate work, since we only judge whether
input value is 0 or not, see following code:
"
tbz w1, #0, 1f
dc isw, x9
b 2f
1: dc cisw, x9 /* clean & invalidate by set/way */
2: subs x6, x6, #1 /* decrement the way */
"

Later we may add "2 clean only" support. So following the comments,
correct value from 0xffff to 1.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

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remove unnecessary version.h includes

Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off

remove unnecessary version.h includes

Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack

Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flus

armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack

Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.

Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.

Signed-off-by: York Sun <yorksun@freescale.com>

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ARM: armv8: Fix typo in commentary

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

ARMv8: fix bug for flush data cache by set/way

When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula

ARMv8: fix bug for flush data cache by set/way

When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula to calculate the offset: log2(Associativity * 2 - 1), so finally
it cannot flush data cache properly.

Signed-off-by: Leo Yan <leoy@marvell.com>

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armv8/cache: Change cache invalidate and flush function

When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wr

armv8/cache: Change cache invalidate and flush function

When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wrapper.

Invalidating large cache can ben slow on emulator, so we postpone doing
so until I-cache is enabled, and before enabling D-cache.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Merge branch 'master' of git://git.denx.de/u-boot-arm

Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
include/configs/ex

Merge branch 'master' of git://git.denx.de/u-boot-arm

Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>

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arm64: core support

Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>