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23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
41 reg = <0x0 0x21c0500 0x0 0x100>;
49 reg = <0x0 0x21c0600 0x0 0x100>;
64 reg = <0x0 0x2100000 0x0 0x10000>;
73 reg = <0x0 0x20c0000 0x0 0x10000>,
74 <0x0 0x20000000 0x0 0x10000000>;
81 reg = <0x0 0x3100000 0x0 0x10000>;
88 reg = <0x0 0x3110000 0x0 0x10000>;
95 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
96 0x00 0x03480000 0x0 0x80000 /* lut registers */
97 0x10 0x00000000 0x0 0x20000>; /* configuration space */
103 bus-range = <0x0 0xff>;
104 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
105 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
110 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
111 0x00 0x03580000 0x0 0x80000 /* lut registers */
112 0x12 0x00000000 0x0 0x20000>; /* configuration space */
118 bus-range = <0x0 0xff>;
119 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
120 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
125 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
126 0x00 0x03680000 0x0 0x80000 /* lut registers */
127 0x14 0x00000000 0x0 0x20000>; /* configuration space */
133 bus-range = <0x0 0xff>;
134 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
135 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
140 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
141 0x00 0x03780000 0x0 0x80000 /* lut registers */
142 0x16 0x00000000 0x0 0x20000>; /* configuration space */
148 bus-range = <0x0 0xff>;
149 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */