| #
9563e87b |
| 27-Jul-2018 |
Zhihuan He <huan.he@rock-chips.com> |
ARM64: invalid icache for cortex a35
Different loader can not boot normally in cortex-A35,like rk3308,
because cortex-A35 enable icache in default.
Change-Id: I87f3e8a2539186f3e408fad8ea903c375118b
ARM64: invalid icache for cortex a35
Different loader can not boot normally in cortex-A35,like rk3308,
because cortex-A35 enable icache in default.
Change-Id: I87f3e8a2539186f3e408fad8ea903c375118b1d9
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
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|
| #
c1da286a |
| 10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
v
UPSTREAM: arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers. One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.
To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.
Change-Id: I9403d28218f03cdf84b1e8cbd4d3d4eef790e9b9
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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|