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Searched refs:timing (Results 1 – 25 of 128) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/
H A Datmel_lcdfb.c33 struct display_timing timing; member
115 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, in atmel_fb_init() argument
135 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
141 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
142 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
157 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_fb_init()
159 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) in atmel_fb_init()
165 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; in atmel_fb_init()
166 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; in atmel_fb_init()
167 value |= timing->vfront_porch.typ; in atmel_fb_init()
[all …]
H A Datmel_hlcdfb.c255 struct display_timing timing; member
295 struct display_timing *timing = &priv->timing; in atmel_hlcdc_init() local
326 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
327 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
331 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) in atmel_hlcdc_init()
358 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_hlcdc_init()
360 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) in atmel_hlcdc_init()
386 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1); in atmel_hlcdc_init()
387 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1); in atmel_hlcdc_init()
390 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); in atmel_hlcdc_init()
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H A Ddisplay-uclass.c23 const struct display_timing *timing) in display_enable() argument
31 ret = ops->enable(dev, panel_bpp, timing); in display_enable()
41 int display_read_timing(struct udevice *dev, struct display_timing *timing) in display_read_timing() argument
49 return ops->read_timing(dev, timing); in display_read_timing()
57 return edid_get_timing(buf, ret, timing, &panel_bits_per_colour); in display_read_timing()
H A Dtegra.c30 struct display_timing timing; member
103 struct display_timing *dt = &priv->timing; in update_display_mode()
340 struct display_timing *timing; in tegra_lcd_ofdata_to_platdata() local
359 ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); in tegra_lcd_ofdata_to_platdata()
365 timing = &priv->timing; in tegra_lcd_ofdata_to_platdata()
366 priv->width = timing->hactive.typ; in tegra_lcd_ofdata_to_platdata()
367 priv->height = timing->vactive.typ; in tegra_lcd_ofdata_to_platdata()
368 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_ofdata_to_platdata()
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddisplay.c28 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
33 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
34 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
35 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
36 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
46 static void print_mode(const struct display_timing *timing) in print_mode() argument
48 int refresh = tegra_dc_calc_refresh(timing); in print_mode()
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
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H A Ddp.c485 const struct display_timing *timing, in tegra_dc_dp_calc_config() argument
510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
514 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
518 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, in tegra_dc_dp_calc_config()
519 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
521 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
601 num_symbols_per_line = (timing->hactive.typ * in tegra_dc_dp_calc_config()
622 link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ + in tegra_dc_dp_calc_config()
623 timing->hfront_porch.typ + timing->hsync_len.typ - 7) * in tegra_dc_dp_calc_config()
624 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
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/rk3399_rockchip-uboot/drivers/mmc/
H A Dxenon_sdhci.c112 u8 timing; member
130 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
131 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_init()
132 (priv->timing == MMC_TIMING_UHS_SDR12) || in xenon_mmc_phy_init()
133 (priv->timing == MMC_TIMING_SD_HS) || in xenon_mmc_phy_init()
134 (priv->timing == MMC_TIMING_LEGACY)) in xenon_mmc_phy_init()
219 if ((priv->timing == MMC_TIMING_MMC_HS400) || in xenon_mmc_phy_set()
220 (priv->timing == MMC_TIMING_MMC_HS200) || in xenon_mmc_phy_set()
221 (priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_set()
222 (priv->timing == MMC_TIMING_UHS_SDR104) || in xenon_mmc_phy_set()
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H A Dsdhci.c446 u32 timing = host->mmc->timing; local
452 if ((timing != MMC_TIMING_LEGACY) &&
453 (timing != MMC_TIMING_MMC_HS) &&
454 (timing != MMC_TIMING_SD_HS))
457 if ((timing == MMC_TIMING_MMC_HS200) ||
458 (timing == MMC_TIMING_UHS_SDR104))
460 else if (timing == MMC_TIMING_UHS_SDR12)
462 else if (timing == MMC_TIMING_UHS_SDR25)
464 else if ((timing == MMC_TIMING_UHS_SDR50) ||
465 (timing == MMC_TIMING_MMC_HS))
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/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_mipi.c30 struct display_timing *timing) in rk_mipi_read_timing() argument
35 0, timing); in rk_mipi_read_timing()
80 const struct display_timing *timing) in rk_mipi_dsi_enable() argument
92 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
93 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
94 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
95 + timing->hback_porch.typ + timing->hactive.typ in rk_mipi_dsi_enable()
96 + timing->hfront_porch.typ)); in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
98 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
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H A Drk_mipi.h24 struct display_timing *timing);
27 const struct display_timing *timing);
H A Drk_vop.c228 struct display_timing timing; in rk_display_init() local
274 ret = display_read_timing(disp, &timing); in rk_display_init()
282 ret = clk_set_rate(&clk, timing.pixelclock.typ); in rk_display_init()
302 rkvop_mode_set(dev, &timing, vop_id); in rk_display_init()
303 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); in rk_display_init()
305 ret = display_enable(disp, 1 << l2bpp, &timing); in rk_display_init()
309 uc_priv->xsize = timing.hactive.typ; in rk_display_init()
310 uc_priv->ysize = timing.vactive.typ; in rk_display_init()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dinno_mipi_phy.c306 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
310 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
311 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
312 timing->clkpre = 8 * period; in mipi_dphy_timing_get_default()
313 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
314 timing->clksettle = 95; in mipi_dphy_timing_get_default()
315 timing->clktermen = 0; in mipi_dphy_timing_get_default()
316 timing->clktrail = 80; in mipi_dphy_timing_get_default()
317 timing->clkzero = 260; in mipi_dphy_timing_get_default()
318 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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H A Dinno_video_combo_phy.c357 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
361 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
362 timing->clkpost = 70000 + 52 * period; in mipi_dphy_timing_get_default()
363 timing->clkpre = 8 * period; in mipi_dphy_timing_get_default()
364 timing->clkprepare = 65000; in mipi_dphy_timing_get_default()
365 timing->clksettle = 95000; in mipi_dphy_timing_get_default()
366 timing->clktermen = 0; in mipi_dphy_timing_get_default()
367 timing->clktrail = 80000; in mipi_dphy_timing_get_default()
368 timing->clkzero = 260000; in mipi_dphy_timing_get_default()
369 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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H A Dsamsung_mipi_dcphy.c1340 const struct samsung_mipi_dphy_timing *timing; in samsung_mipi_dphy_clk_lane_timing_init() local
1344 timing = samsung_mipi_dphy_get_timing(samsung); in samsung_mipi_dphy_clk_lane_timing_init()
1368 val |= T_LPX(timing->lpx); in samsung_mipi_dphy_clk_lane_timing_init()
1372 val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare); in samsung_mipi_dphy_clk_lane_timing_init()
1375 val = T_HS_EXIT(timing->hs_exit) | T_CLK_TRAIL(timing->clk_trail_eot); in samsung_mipi_dphy_clk_lane_timing_init()
1378 val = T_CLK_POST(timing->clk_post); in samsung_mipi_dphy_clk_lane_timing_init()
1395 const struct samsung_mipi_dphy_timing *timing; in samsung_mipi_dphy_data_lane_timing_init() local
1399 timing = samsung_mipi_dphy_get_timing(samsung); in samsung_mipi_dphy_data_lane_timing_init()
1429 val |= T_LPX(timing->lpx); in samsung_mipi_dphy_data_lane_timing_init()
1436 val = T_HS_ZERO(timing->hs_zero) | T_HS_PREPARE(timing->hs_prepare); in samsung_mipi_dphy_data_lane_timing_init()
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/rk3399_rockchip-uboot/drivers/ram/
H A Dstm32_sdram.c159 struct stm32_sdram_timing *timing; in stm32_sdram_init() local
172 timing = params->bank_params[i].sdram_timing; in stm32_sdram_init()
194 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
195 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
196 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
197 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
198 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
199 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
200 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
204 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
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/rk3399_rockchip-uboot/drivers/usb/host/
H A Dehci-tegra.c305 const unsigned *timing; in get_pll_timing() local
307 timing = controller->pll_parameter + in get_pll_timing()
310 return timing; in get_pll_timing()
353 const unsigned *timing; in init_utmi_usb_controller() local
390 timing = get_pll_timing(controller); in init_utmi_usb_controller()
395 timing[PARAM_STABLE_COUNT] << in init_utmi_usb_controller()
398 timing[PARAM_ACTIVE_DELAY_COUNT] << in init_utmi_usb_controller()
405 timing[PARAM_ENABLE_DELAY_COUNT] << in init_utmi_usb_controller()
408 timing[PARAM_XTAL_FREQ_COUNT] << in init_utmi_usb_controller()
416 timing[PARAM_STABLE_COUNT] << in init_utmi_usb_controller()
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/rk3399_rockchip-uboot/include/
H A Ddisplay.h33 int display_read_timing(struct udevice *dev, struct display_timing *timing);
44 const struct display_timing *timing);
62 int (*read_timing)(struct udevice *dev, struct display_timing *timing);
83 const struct display_timing *timing);
/rk3399_rockchip-uboot/board/samsung/common/
H A Dboard.c191 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, in decode_sromc()
237 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | in board_eth_init()
238 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | in board_eth_init()
239 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | in board_eth_init()
240 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | in board_eth_init()
241 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | in board_eth_init()
242 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | in board_eth_init()
243 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); in board_eth_init()
/rk3399_rockchip-uboot/doc/device-tree-bindings/ram/
H A Dst,stm32-fmc.txt18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Ddisplay-timing.txt1 display-timing bindings
14 timing subnode
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
99 timing1: timing {
/rk3399_rockchip-uboot/drivers/mtd/
H A Dftsmc020.c15 unsigned int timing; member
28 writel(cfg->timing, &smc->bank[bank].tpr); in ftsmc020_setup_bank()
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt27 rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet
50 rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
51 rockchip,trp: tRP,AC timing parameters from the memory data-sheet
53 -rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
88 -rockchip,phy-timing: PHY timing information in this order:
104 NOC timing - value for ddrtiming register
146 rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa
151 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
/rk3399_rockchip-uboot/drivers/misc/
H A Dmxc_ocotp.c248 u32 timing; in set_timing() local
256 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); in set_timing()
258 clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, in set_timing()
259 timing); in set_timing()
272 u32 timing; in set_timing() local
282 timing = BF(strobe_read, TIMING_STROBE_READ) | in set_timing()
286 clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | in set_timing()
287 BM_TIMING_STROBE_PROG, timing); in set_timing()
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_display.c210 (struct edid_detailed_timing *)edid1.monitor_details.timing; in sunxi_hdmi_edid_get_mode()
726 struct display_timing *timing) in sunxi_ctfb_mode_to_display_timing() argument
728 timing->pixelclock.typ = mode->pixclock_khz * 1000; in sunxi_ctfb_mode_to_display_timing()
730 timing->hactive.typ = mode->xres; in sunxi_ctfb_mode_to_display_timing()
731 timing->hfront_porch.typ = mode->right_margin; in sunxi_ctfb_mode_to_display_timing()
732 timing->hback_porch.typ = mode->left_margin; in sunxi_ctfb_mode_to_display_timing()
733 timing->hsync_len.typ = mode->hsync_len; in sunxi_ctfb_mode_to_display_timing()
735 timing->vactive.typ = mode->yres; in sunxi_ctfb_mode_to_display_timing()
736 timing->vfront_porch.typ = mode->lower_margin; in sunxi_ctfb_mode_to_display_timing()
737 timing->vback_porch.typ = mode->upper_margin; in sunxi_ctfb_mode_to_display_timing()
[all …]
H A Dsunxi_de2.c182 struct display_timing timing; in sunxi_de2_init() local
202 ret = display_read_timing(disp, &timing); in sunxi_de2_init()
209 sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite); in sunxi_de2_init()
211 ret = display_enable(disp, 1 << l2bpp, &timing); in sunxi_de2_init()
217 uc_priv->xsize = timing.hactive.typ; in sunxi_de2_init()
218 uc_priv->ysize = timing.vactive.typ; in sunxi_de2_init()

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