485 				   const struct display_timing *timing,  in tegra_dc_dp_calc_config()  argument
510 	if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ ||  in tegra_dc_dp_calc_config()
514 	if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >=  in tegra_dc_dp_calc_config()
518 	num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ,  in tegra_dc_dp_calc_config()
519 				       timing->pixelclock.typ));  in tegra_dc_dp_calc_config()
521 	ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f;  in tegra_dc_dp_calc_config()
601 	num_symbols_per_line = (timing->hactive.typ *  in tegra_dc_dp_calc_config()
622 	link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ +  in tegra_dc_dp_calc_config()
623 			timing->hfront_porch.typ + timing->hsync_len.typ - 7) *  in tegra_dc_dp_calc_config()
624 			link_rate, timing->pixelclock.typ) -  in tegra_dc_dp_calc_config()
639 	link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25)  in tegra_dc_dp_calc_config()
640 			* link_rate, timing->pixelclock.typ) - (36 /  in tegra_dc_dp_calc_config()
655 			const struct display_timing *timing,  in tegra_dc_dp_init_max_link_cfg()  argument
715 	tegra_dc_dp_calc_config(dp, timing, link_cfg);  in tegra_dc_dp_init_max_link_cfg()
983 				      const struct display_timing *timing,  in tegra_dp_lower_link_config()  argument
994 		ret = tegra_dc_dp_calc_config(dp, timing, cfg);  in tegra_dp_lower_link_config()
1192 					  const struct display_timing *timing,  in tegra_dc_dp_full_link_training()  argument
1208 		if (!tegra_dp_lower_link_config(dp, timing, cfg))  in tegra_dc_dp_full_link_training()
1217 		if (!tegra_dp_lower_link_config(dp, timing, cfg))  in tegra_dc_dp_full_link_training()
1309 		const struct display_timing *timing,  in tegra_dp_do_link_training()  argument
1334 		ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg);  in tegra_dp_do_link_training()
1354 			const struct display_timing *timing)  in tegra_dc_dp_explore_link_cfg()  argument
1358 	if (!timing->pixelclock.typ || !timing->hactive.typ ||  in tegra_dc_dp_explore_link_cfg()
1359 	    !timing->vactive.typ) {  in tegra_dc_dp_explore_link_cfg()
1378 	if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) &&  in tegra_dc_dp_explore_link_cfg()
1380 		(!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor)))  in tegra_dc_dp_explore_link_cfg()
1427 				  const struct display_timing *timing)  in tegra_dc_dp_check_sink()  argument
1457 						 timing)) {  in tegra_dc_dp_check_sink()
1463 		tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);  in tegra_dc_dp_check_sink()
1472 		    const struct display_timing *timing)  in tegra_dp_enable()  argument
1493 	if (tegra_dc_dp_init_max_link_cfg(timing, priv, link_cfg)) {  in tegra_dp_enable()
1536 	if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) {  in tegra_dp_enable()
1542 	ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);  in tegra_dp_enable()
1551 		ret = tegra_dc_dp_check_sink(priv, link_cfg, timing);  in tegra_dp_enable()