| #
90aa625c |
| 16-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in include/linux/compiler-gcc.h
treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl> @@@@ -error +pr_err (...) // </smpl>
Change-Id: I921807c1770d36a91e692c48ab477558bb2ed0b8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> (cherry picked from commit 9b643e312d528f291966c1f30b0d90bf3b1d43dc)
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| #
7016651e |
| 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: add stm32h7 support
STM32F7 and H7 shared the same SDRAM control block. On STM32H7 few control bits has been added. The current driver need some minor adaptation as FMC block enable/disa
ram: stm32: add stm32h7 support
STM32F7 and H7 shared the same SDRAM control block. On STM32H7 few control bits has been added. The current driver need some minor adaptation as FMC block enable/disable for H7.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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| #
f303aaf2 |
| 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some
ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some bank1 registers must be configured.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
f39b90dc |
| 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: replace fdtdec_get by ofnode calls
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..(). This will allow drivers to support a live device tree.
Signed-off-by: Patrice Ch
ram: stm32: replace fdtdec_get by ofnode calls
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..(). This will allow drivers to support a live device tree.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
1421e0a3 |
| 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: get base address from DT
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM registers are located at offset
ram: stm32: get base address from DT
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM registers are located at offset 0x140 inside FMC block. Update the stm32_fmc_regs fields with all FMC registers to map SDRAM registers at the right address.
These additionals registers will be used later.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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| #
9242ece1 |
| 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: migrate fmc defines in driver file
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/f
ram: stm32: migrate fmc defines in driver file
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
14a50e37 |
| 30-May-2017 |
Patrice Chotard <patrice.chotard@st.com> |
drivers: ram: stm32: fix compilation issue
If CONFIG_CLK flag is not set, compilation raises the following error message:
drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe': drivers/ram/stm32
drivers: ram: stm32: fix compilation issue
If CONFIG_CLK flag is not set, compilation raises the following error message:
drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe': drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function) ret = stm32_sdram_init(dev);
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> cc: Vikas Manocha <vikas.manocha@st.com>
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| #
da409ccc |
| 17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live devi
dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
4f66e09b |
| 09-May-2017 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| #
bfea69ad |
| 10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: sdram: correct sdram configuration as per micron sdram
Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required i
stm32f7: sdram: correct sdram configuration as per micron sdram
Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required in the device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
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| #
57af3cc3 |
| 10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: stm32f746-disco: read memory info from device tree
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
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| #
6c9a1003 |
| 10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: sdram: use sdram device tree node to configure sdram controller
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
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| #
d0b24c1a |
| 10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use clock driver to enable sdram controller clock
This patch also removes the sdram/fmc clock enable from board specific code.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Chris
stm32f7: use clock driver to enable sdram controller clock
This patch also removes the sdram/fmc clock enable from board specific code.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
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| #
910a52ed |
| 10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: dm: add driver model support for sdram
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
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| #
bf1ae442 |
| 10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: sdram: move sdram driver code to ram drivers area
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
|