mmc: sdhci: add function sdhci_enable_clk

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I8b738489a5094acb74749b9e9afd3999d6ca0571

Revert "mmc: sdhci: add execute_tuning_end api for RK3528 to support HS400"

This reverts commit 59b2bce9b7f26ba45a588a67a1a03ea44b694376.

Change-Id: Ia6d7ee42260009253098b4764ba6eab5e0029b71
Signed

Revert "mmc: sdhci: add execute_tuning_end api for RK3528 to support HS400"

This reverts commit 59b2bce9b7f26ba45a588a67a1a03ea44b694376.

Change-Id: Ia6d7ee42260009253098b4764ba6eab5e0029b71
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>

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drivers: mmc: sdhci: solve the problem of dead cycle

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I95170d896aee9fb8f6e5af673b993d53e312b43c

mmc: sdhci: add execute_tuning_end api for RK3528 to support HS400

The rxclk tap tuning by HS200 mode is unsuited for HS400 mode,
in addition, when switching from HS200 mode to HS mode, errors
may o

mmc: sdhci: add execute_tuning_end api for RK3528 to support HS400

The rxclk tap tuning by HS200 mode is unsuited for HS400 mode,
in addition, when switching from HS200 mode to HS mode, errors
may occur while sending commands.
It need to manually configure rxclk tap, and disable the tuning
parameter while in hs mode.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I7bb3e4fcf19aa0a80fca74122a2c1b3d81dbf361

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mmc: rockchip: support hs400es mode

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I5c80afca7cdd5616935f65914872a972c892c775

mmc: sdhci: clean INT STATUS while wait CMD_INHIBIT timeout

There is a very low probability for waiting "CMD_INHIBIT" timeout.
It is necessary to clear INT STATUS after timeout and do not
return err

mmc: sdhci: clean INT STATUS while wait CMD_INHIBIT timeout

There is a very low probability for waiting "CMD_INHIBIT" timeout.
It is necessary to clear INT STATUS after timeout and do not
return error after timeout for best compatibility.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I8987eab046cc5eb8b9a9abd28bae1cfd92e107fa

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mmc: sdhci: don't clear SDHCI_INT_STATUS register during CMD_INHIBIT

Fixes emmc initialization regression on the db410c platform.

Clearing this register while SDHCI_PRESENT_STATE reports
SDHCI_CMD_

mmc: sdhci: don't clear SDHCI_INT_STATUS register during CMD_INHIBIT

Fixes emmc initialization regression on the db410c platform.

Clearing this register while SDHCI_PRESENT_STATE reports
SDHCI_CMD_INHIBIT leads to undefined behaviour on the db410c.

When commit 7dde50 was merged (mmc: sdhci: Wait for SDHCI_INT_DATA_END
when transferring), SDHCI transfers transitioned to wait for bit
SDHCI_INT_DATA_END before flagging transfers done.

Without this patch, the db410 platform fails to initialize its eMMC
due to all of its transfers timing out (SDHCI_INT_DATA_END is never
raised after all the blocks have been transferred).

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Change-Id: I9aaca0e60ed042a99d325d7a35fa2794a73c0cb6
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>

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mmc: sdhci: config controller MMC_TIMING_MMC_HS

If emmc driver config MMC_TIMING_MMC_HS, need config

controller SDHCI_HOST_CONTROL2 register SDHCI_CTRL_UHS_SDR50.

It will affect emmc phy work mode

mmc: sdhci: config controller MMC_TIMING_MMC_HS

If emmc driver config MMC_TIMING_MMC_HS, need config

controller SDHCI_HOST_CONTROL2 register SDHCI_CTRL_UHS_SDR50.

It will affect emmc phy work mode.

Change-Id: Ib45f30eb6b70bde6f1beb4612ded17ee2b24b5fe
Signed-off-by: chenfen <chenfen@rock-chips.com>

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mmc: sdhci: add the support for tuning

MMC framework has already implemented hs200 mode for eMMC devices,
moreover the standard SDHC3.0 controller support tuning. We can set the
corresponding flag i

mmc: sdhci: add the support for tuning

MMC framework has already implemented hs200 mode for eMMC devices,
moreover the standard SDHC3.0 controller support tuning. We can set the
corresponding flag in host->host_cpas.

Host driver issue tuning command repeatedly until the host controller
resets Execute Tuning to 0. Host controller resets Execute Tuning to 0
when tuning is completed or tuning is not completed within 40 times.
Host driver can abort this loop by 40 times CMD19/CMD21 issue or 150ms
time-out. If tuning is completed successfully, driver set Sampling Clock
Select to 1 and this means the host contorller start to use tuned
sampling clcok. If tuning is failed, host controller keeps Sampling
Clock Select to 0.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

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mmc: sdhci: export sdhci_set_clock()

For arasan-rk3399-sdhci controller, we should make sure the phy is in
poweroff status before we configure the clock stuff. So that we need to
export it for phy c

mmc: sdhci: export sdhci_set_clock()

For arasan-rk3399-sdhci controller, we should make sure the phy is in
poweroff status before we configure the clock stuff. So that we need to
export it for phy configuration.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

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mmc: sdhci: rename set_clock callback

In fact, the original name is unsuitable for its behavior. It's better
to rename to set_clock_ext.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

mmc: sdhci: add support for UHS timing

To support UHS speed mode, controller should enable 1.8V signaling and
select one of UHS modes.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

mmc: sdhci: update host->clock after clock setting

Overwrite host->clock after clock setting to avoid repetitive reset
clock.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

mmc: sdhci: implement card_busy detection

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

mmc: sdhci: fix HISPD bit setting

Configure HISPD bit field according to the timing parameter instead of
the card clock frequency.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

Merge branch 'master' of git://git.denx.de/u-boot-mmc

dm: mmc: Drop CONFIG_DM_MMC_OPS

All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>

Merge branch 'master' of git://git.denx.de/u-boot-mmc

- Add #undef CONFIG_DM_MMC_OPS to omap3_logic in the SPL build case, to
match other TI platforms in the same situation.

Signed-off-by: Tom Ri

Merge branch 'master' of git://git.denx.de/u-boot-mmc

- Add #undef CONFIG_DM_MMC_OPS to omap3_logic in the SPL build case, to
match other TI platforms in the same situation.

Signed-off-by: Tom Rini <trini@konsulko.com>

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mmc: sdhci: Fix maximum clock for programmable clock mode

In the programmable clock mode, the SDCLK frequency is incorrectly
assigned when the maximum clock has been assigned during probe,
this caus

mmc: sdhci: Fix maximum clock for programmable clock mode

In the programmable clock mode, the SDCLK frequency is incorrectly
assigned when the maximum clock has been assigned during probe,
this causes the SDHCI not work well.

In the programmable clock mode, when calculating the SDCLK Frequency
Select, when the maximum clock has been assigned, it is the actual
value, should not be multiplied by host->clk_mul. Otherwise, the
maximum clock is multiplied host->clk_mul by the base clock achieved
from the BASECLKF field of the Capabilities 0 Register.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mmc

mmc: sdhci: Wait for SDHCI_INT_DATA_END when transferring.

sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all

mmc: sdhci: Wait for SDHCI_INT_DATA_END when transferring.

sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all
the blocks are transferred, even if the loop exit condition is not met
(bit SDHCI_INT_DATA_END set in the STATUS word).

When doing multiple writes to mmc, returning right after the last block
is transferred can cause the write to fail when sending the
MMC_CMD_STOP_TRANSMISSION command right after the
MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
unconsistent state until reboot. This error was observed in the rpi3
board.

This patch waits for the SDHCI_INT_DATA_END bit to be set even after
sending all the blocks.

Test: Reliably wrote 2GiB of data to mmc in a rpi3.

Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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mmc: sdhci: only flush cache for data command

No need to flush cache for command without data.

Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>

Merge branch 'master' of git://git.denx.de/u-boot-mmc

mmc: sdhci: only flush cache for data command

No need to flush cache for command without data.

Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>

Merge git://www.denx.de/git/u-boot-marvell