210 		(struct edid_detailed_timing *)edid1.monitor_details.timing;  in sunxi_hdmi_edid_get_mode()
726 					      struct display_timing *timing)  in sunxi_ctfb_mode_to_display_timing()  argument
728 	timing->pixelclock.typ = mode->pixclock_khz * 1000;  in sunxi_ctfb_mode_to_display_timing()
730 	timing->hactive.typ = mode->xres;  in sunxi_ctfb_mode_to_display_timing()
731 	timing->hfront_porch.typ = mode->right_margin;  in sunxi_ctfb_mode_to_display_timing()
732 	timing->hback_porch.typ = mode->left_margin;  in sunxi_ctfb_mode_to_display_timing()
733 	timing->hsync_len.typ = mode->hsync_len;  in sunxi_ctfb_mode_to_display_timing()
735 	timing->vactive.typ = mode->yres;  in sunxi_ctfb_mode_to_display_timing()
736 	timing->vfront_porch.typ = mode->lower_margin;  in sunxi_ctfb_mode_to_display_timing()
737 	timing->vback_porch.typ = mode->upper_margin;  in sunxi_ctfb_mode_to_display_timing()
738 	timing->vsync_len.typ = mode->vsync_len;  in sunxi_ctfb_mode_to_display_timing()
741 		timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;  in sunxi_ctfb_mode_to_display_timing()
743 		timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;  in sunxi_ctfb_mode_to_display_timing()
745 		timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;  in sunxi_ctfb_mode_to_display_timing()
747 		timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;  in sunxi_ctfb_mode_to_display_timing()
749 		timing->flags |= DISPLAY_FLAGS_INTERLACED;  in sunxi_ctfb_mode_to_display_timing()
758 	struct display_timing timing;  local
778 	sunxi_ctfb_mode_to_display_timing(mode, &timing);
779 	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
790 	struct display_timing timing;  local
792 	sunxi_ctfb_mode_to_display_timing(mode, &timing);
793 	lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,