1fd198ee1SVikas ManochaST, stm32 flexible memory controller Drive 2fd198ee1SVikas ManochaRequired properties: 3fd198ee1SVikas Manocha- compatible : "st,stm32-fmc" 4fd198ee1SVikas Manocha- reg : fmc controller base address 5fd198ee1SVikas Manocha- clocks : fmc controller clock 6fd198ee1SVikas Manochau-boot,dm-pre-reloc: flag to initialize memory before relocation. 7fd198ee1SVikas Manocha 8fd198ee1SVikas Manochaon-board sdram memory attributes: 9fd198ee1SVikas Manocha- st,sdram-control : parameters for sdram configuration, in this order: 10fd198ee1SVikas Manocha number of columns 11fd198ee1SVikas Manocha number of rows 12fd198ee1SVikas Manocha memory width 13fd198ee1SVikas Manocha number of intenal banks in memory 14fd198ee1SVikas Manocha cas latency 15fd198ee1SVikas Manocha read burst enable or disable 16fd198ee1SVikas Manocha read pipe delay 17fd198ee1SVikas Manocha 18fd198ee1SVikas Manocha- st,sdram-timing: timings for sdram, in this order: 19fd198ee1SVikas Manocha tmrd 20fd198ee1SVikas Manocha txsr 21fd198ee1SVikas Manocha tras 22fd198ee1SVikas Manocha trc 23fd198ee1SVikas Manocha trp 24fd198ee1SVikas Manocha trcd 25fd198ee1SVikas Manocha 26fd198ee1SVikas ManochaThere is device tree include file at : 27fd198ee1SVikas Manochainclude/dt-bindings/memory/stm32-sdram.h to define sdram control and timing 28fd198ee1SVikas Manochaparameters as MACROS. 29fd198ee1SVikas Manocha 30fd198ee1SVikas ManochaExample: 31fd198ee1SVikas Manocha fmc: fmc@A0000000 { 32fd198ee1SVikas Manocha compatible = "st,stm32-fmc"; 33fd198ee1SVikas Manocha reg = <0xA0000000 0x1000>; 34fd198ee1SVikas Manocha clocks = <&rcc 0 64>; 35fd198ee1SVikas Manocha u-boot,dm-pre-reloc; 36fd198ee1SVikas Manocha }; 37fd198ee1SVikas Manocha 38fd198ee1SVikas Manocha &fmc { 39fd198ee1SVikas Manocha pinctrl-0 = <&fmc_pins>; 40fd198ee1SVikas Manocha pinctrl-names = "default"; 41fd198ee1SVikas Manocha status = "okay"; 42fd198ee1SVikas Manocha 43fd198ee1SVikas Manocha /* sdram memory configuration from sdram datasheet */ 44fd198ee1SVikas Manocha bank1: bank@0 { 45fd198ee1SVikas Manocha st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 46fd198ee1SVikas Manocha CAS_3 RD_BURST_EN RD_PIPE_DL_0>; 47fd198ee1SVikas Manocha st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 48fd198ee1SVikas Manocha TRCD_18>; 49fd198ee1SVikas Manocha }; 50*f303aaf2SPatrice Chotard 51*f303aaf2SPatrice Chotard /* sdram memory configuration from sdram datasheet */ 52*f303aaf2SPatrice Chotard bank2: bank@1 { 53*f303aaf2SPatrice Chotard st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 54*f303aaf2SPatrice Chotard CAS_3 RD_BURST_EN RD_PIPE_DL_0>; 55*f303aaf2SPatrice Chotard st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 56*f303aaf2SPatrice Chotard TRCD_18>; 57*f303aaf2SPatrice Chotard }; 58fd198ee1SVikas Manocha } 59