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Searched refs:reg_offset (Results 1 – 25 of 25) sorted by relevance

/rk3399_rockchip-uboot/drivers/power/pmic/
H A Dpmic_tps65910.c44 unsigned int reg_offset; in tps65910_voltage_update() local
48 reg_offset = TPS65910_VDD1_OP_REG; in tps65910_voltage_update()
50 reg_offset = TPS65910_VDD2_OP_REG; in tps65910_voltage_update()
53 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
59 ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
64 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
71 ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
75 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
H A Drk8xx.c22 .reg_offset = 0,
26 .reg_offset = 0,
30 .reg_offset = 0,
48 .reg_offset = 0,
52 .reg_offset = 0,
71 .reg_offset = 1,
75 .reg_offset = 0,
94 .reg_offset = 0,
98 .reg_offset = 0,
102 .reg_offset = 2,
[all …]
H A Dpmic_rk801.c20 .reg_offset = 0,
24 .reg_offset = 0,
H A Drk8xx_spi.c22 .reg_offset = 0,
26 .reg_offset = 0,
/rk3399_rockchip-uboot/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c52 int reg_offset; in mvebu_pinctrl_set_state() local
63 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state()
67 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
101 int reg_offset; in mvebu_pinctrl_set_state_all() local
116 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state_all()
120 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dfsl_liodn.h14 unsigned long reg_offset[2]; member
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
28 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
44 unsigned long reg_offset; member
56 unsigned long reg_offset; member
73 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
80 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
87 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
/rk3399_rockchip-uboot/board/siemens/pxm2/
H A Dboard.c96 unsigned int reg_offset; in voltage_update() local
99 reg_offset = PMIC_VDD1_OP_REG; in voltage_update()
101 reg_offset = PMIC_VDD2_OP_REG; in voltage_update()
104 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
109 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
113 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
119 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
122 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/
H A Dmux.c31 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) in configure_module_pin_mux()
32 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); in configure_module_pin_mux()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_stream_id.h15 .reg_offset = off + CONFIG_SYS_IMMR, \
22 .reg_offset = off + CONFIG_SYS_IMMR, \
63 unsigned long reg_offset; member
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dliodn.c33 unsigned long reg_off = tbl[i].reg_offset[0]; in set_srio_liodn()
37 reg_off = tbl[i].reg_offset[1]; in set_srio_liodn()
56 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_liodn()
72 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_fman_liodn()
164 out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]); in set_rman_liodn()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-am33xx/
H A Dmux.h33 short reg_offset; member
/rk3399_rockchip-uboot/drivers/gpio/
H A Dzynq_gpio.c223 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
234 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
236 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
247 writel(value, priv->base + reg_offset); in zynq_gpio_set_value()
/rk3399_rockchip-uboot/board/freescale/common/
H A Dls102xa_stream_id.c34 out_le32((u32 *)(tbl[i].reg_offset), liodn); in ls1021x_config_caam_stream_id()
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_intel_mid.c32 writel(value, addr + plat->reg_offset); in mid_writel()
H A Dns16550.c106 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
117 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); in ns16550_readb()
571 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in ns16550_serial_ofdata_to_platdata()
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_engine.c595 u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg; in ddr3_tip_read_training_result() local
680 for (reg_offset = start_reg; reg_offset <= end_reg; in ddr3_tip_read_training_result()
681 reg_offset++) { in ddr3_tip_read_training_result()
688 reg_addr[reg_offset], in ddr3_tip_read_training_result()
695 [reg_offset] = in ddr3_tip_read_training_result()
700 [reg_offset] = in ddr3_tip_read_training_result()
706 interface_train_res[reg_offset] in ddr3_tip_read_training_result()
713 reg_offset, in ddr3_tip_read_training_result()
715 [reg_offset], in ddr3_tip_read_training_result()
717 [reg_offset])); in ddr3_tip_read_training_result()
/rk3399_rockchip-uboot/drivers/net/
H A Dsh_eth.h661 const u16 *reg_offset = sh_eth_offset_gigabit; in sh_eth_reg_addr() local
663 const u16 *reg_offset = sh_eth_offset_fast_sh4; in sh_eth_reg_addr()
665 const u16 *reg_offset = sh_eth_offset_rz; in sh_eth_reg_addr()
669 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; in sh_eth_reg_addr()
H A Dmvgbe.c329 u32 reg_offset; in port_uc_addr() local
336 reg_offset = uc_nibble % 4; in port_uc_addr()
345 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
351 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
352 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); in port_uc_addr()
H A Dmvneta.c849 unsigned int reg_offset; in mvneta_set_ucast_addr() local
858 reg_offset = last_nibble % 4; in mvneta_set_ucast_addr()
864 unicast_reg &= ~(0xff << (8 * reg_offset)); in mvneta_set_ucast_addr()
866 unicast_reg &= ~(0xff << (8 * reg_offset)); in mvneta_set_ucast_addr()
867 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); in mvneta_set_ucast_addr()
/rk3399_rockchip-uboot/include/
H A Dirq-generic.h74 uint reg_offset; member
H A Dns16550.h59 int reg_offset; member
/rk3399_rockchip-uboot/drivers/mmc/
H A Domap_hsmmc.c60 u32 reg_offset; member
813 MAP_NOCACHE) + data->reg_offset;
890 .reg_offset = 0,
894 .reg_offset = 0x100,
898 .reg_offset = 0x100,
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_vop2.c1353 u32 reg_offset; member
5268 u32 win_offset = win->reg_offset; in vop2_setup_scale()
5459 u32 win_offset = win->reg_offset; in vop2_axi_config()
5514 u32 win_offset = win->reg_offset; in vop2_set_cluster_win()
5617 u32 win_offset = win->reg_offset; in vop2_set_smart_win()
5629 val = vop2_readl(vop2, RK3568_ESMART0_REGION0_CTRL + source_win->reg_offset); in vop2_set_smart_win()
6660 vop2_cluster_disable(regs, vop2_data->win_data[i].reg_offset); in rockchip_vop2_reset()
6662 vop2_esmart_disable(regs, vop2_data->win_data[i].reg_offset); in rockchip_vop2_reset()
6720 .reg_offset = 0,
6742 .reg_offset = 0x200,
[all …]
H A Ddw_hdmi_qp.c394 u8 reg_offset, val_offset, i; in dw_hdmi_i2c_read() local
398 reg_offset = i / 4; in dw_hdmi_i2c_read()
401 reg_offset; in dw_hdmi_i2c_read()
/rk3399_rockchip-uboot/drivers/irq/
H A Dvirq.c220 if (desc->status_buf[chip->irqs[i].reg_offset] & in virq_chip_generic_handler()
348 chip->irqs[virq].reg_offset); in __virq_enable()