drm/rockchip: vop2: add vop reset when vp is active state

For one VOP dual os environment, the secondary OS maybe reboot without display
disable or SOC global reset, the hardware may be active state

drm/rockchip: vop2: add vop reset when vp is active state

For one VOP dual os environment, the secondary OS maybe reboot without display
disable or SOC global reset, the hardware may be active state, so add this
reset to avoid unexpected issues, one VOP dual os dts config example:

linux dts:
&vop {
iommus = <&vop_mmu1>;
rockchip,share-mode-axi-id = <1>;
rockchip,share-mode-val = <(ROCKCHIP_VOP2_SHARE_MODE_PRIMARY)>;
rockchip,share-mode-vp-mask = <(1 << ROCKCHIP_VOP_VP2)>;
rockchip,share-mode-plane-mask = <(1 << ROCKCHIP_VOP2_ESMART2 | 1 << ROCKCHIP_VOP2_ESMART3)>;
};

android dts:
&vop {
iommus = <&vop_mmu>;
rockchip,share-mode-axi-id = <0>;
rockchip,share-mode-val = <(ROCKCHIP_VOP2_SHARE_MODE_SECONDARY)>;
rockchip,share-mode-vp-mask = <(1 << ROCKCHIP_VOP_VP0 | 1 << ROCKCHIP_VOP_VP1)>;
rockchip,share-mode-plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_CLUSTER1 |
1 << ROCKCHIP_VOP2_ESMART0 | 1 <<ROCKCHIP_VOP2_ESMART1)>;
};

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I276972204c53538932cd653ec131be7f067c7f82

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video/drm: vop2: Don't support to set clk parent in mos

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia9d23b607dde672516877e0ae477d818876b1986
Signed-off-by: Joseph Chen <chenj

video/drm: vop2: Don't support to set clk parent in mos

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia9d23b607dde672516877e0ae477d818876b1986
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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video/drm: vop2: Add support to enable pd and clk for mos

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I48136b34202fe062943d1981db865af05abebc1b

video/drm: vop2: Add &vop2_ops.assign_plane_mask to distinguish between platforms

Change-Id: I38a07eb458ea297d202f3ff9cb0754e17fadf4d0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

video/drm: vop2: Put the cursor plane assignment a little later

For RK3568 and RK3588, to aovid &vop2.vp_plane_mask[].cursor_plane_id
being overwritten by &vop2.data->plane_mask[].cursor_plane_id, w

video/drm: vop2: Put the cursor plane assignment a little later

For RK3568 and RK3588, to aovid &vop2.vp_plane_mask[].cursor_plane_id
being overwritten by &vop2.data->plane_mask[].cursor_plane_id, which
is always 0, the assignment of cursor plane should be placed at the
end of vop2_plane_mask_assign().

For VOP3, put the cursor plane assignment later to maintain the
consistency of adjacent codes.

Fixes: b4fa21dedfd ("video/drm: vop2: modify the check related to the cursor plane")
Change-Id: Id012cb3c88a3fe5bf3965f5e80a9fdacb234de92
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: Initialize primary/cursor plane ids of &vop2.vp_plane_mask[] and &vop2_data.vp_plane_mask[]

The default value of &vop2_vp_plane_mask.primary_plane_id and
&vop2_vp_plane_mask.cursor_

video/drm: vop2: Initialize primary/cursor plane ids of &vop2.vp_plane_mask[] and &vop2_data.vp_plane_mask[]

The default value of &vop2_vp_plane_mask.primary_plane_id and
&vop2_vp_plane_mask.cursor_plane_id should be macro
ROCKCHIP_VOP2_PHY_ID_INVALID((u8)-1) instead of 0.

For VOP3, it should be more reasonable to put the initialization
process to the beginning of vop2_global_initial().

For RK3568/RK3588, Set cursor_plane_id of &vop2_data.vp_plane_mask[]
to ROCKCHIP_VOP2_PHY_ID_INVALID

Change-Id: Icdc0a7d7b4ee994825838ff9b999b79a0dad366a
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: remove redundant config done at set win

1. the config will be set at rockchip_vop2_enable() at the end of
display_logo(), so remove redundant config done at set win;

2. move win en

video/drm: vop2: remove redundant config done at set win

1. the config will be set at rockchip_vop2_enable() at the end of
display_logo(), so remove redundant config done at set win;

2. move win enable at the end of vop2_set_cluster/smart_win() is
more reasonable.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7266281723b64cc57a8a1bacab026708221a9bfd

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video/drm: vop2: add plane_phy_id to the function *_setup_win_dly

Add plane_phy_id mainly to facilitate future expansion.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ic83466a0e7d74b6

video/drm: vop2: add plane_phy_id to the function *_setup_win_dly

Add plane_phy_id mainly to facilitate future expansion.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ic83466a0e7d74b63533a219e8092ed244d4a7687

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video/drm: vop2: Add support rb swap config for plane

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ie2678b21e80e8e82e89e517b19477d4d084f6b62
(cherry picked from commit f3fc06a17dc899bc

video/drm: vop2: Add support rb swap config for plane

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ie2678b21e80e8e82e89e517b19477d4d084f6b62
(cherry picked from commit f3fc06a17dc899bcdfc0dce93753108d53079922)

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video/drm: vop2: Add support to config CSC from BCSH

The BCSH function of the VPs, which support the feature
VOP_FEATURE_POST_CSC, should be implemented with CSC function.

Change-Id: If155cf4313e85

video/drm: vop2: Add support to config CSC from BCSH

The BCSH function of the VPs, which support the feature
VOP_FEATURE_POST_CSC, should be implemented with CSC function.

Change-Id: If155cf4313e851608007fdee585140a95872746d
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: Use write_mask to config gamma AHB for RK3576

As for the reg of gamma AHB configuration, RK3575 has write_mask
while RK3588/RK3562/RK3528 do not.

Change-Id: Iad0575a723bc29588a18d7

video/drm: vop2: Use write_mask to config gamma AHB for RK3576

As for the reg of gamma AHB configuration, RK3575 has write_mask
while RK3588/RK3562/RK3528 do not.

Change-Id: Iad0575a723bc29588a18d7332f473eca2ad7407b
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: Ensure rk3576 sharp/post-scaler/split are mutually exclusive

VOP sharp/post-scaler/split use the same line buffer.
They must be mutually exclusive, otherwise the picture
will displa

video/drm: vop2: Ensure rk3576 sharp/post-scaler/split are mutually exclusive

VOP sharp/post-scaler/split use the same line buffer.
They must be mutually exclusive, otherwise the picture
will display abnormally.

Change-Id: Ib71992b52496f44e28e93ce2c992fa1cfccd2b64
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: Support hdmi dsc bpp below 9

When the dsc bpp is less than 9, hdmi output will flash on TV.
It is speculated that the reason is that pixel rate of sink
decoding is not enough.

Taki

video/drm: vop2: Support hdmi dsc bpp below 9

When the dsc bpp is less than 9, hdmi output will flash on TV.
It is speculated that the reason is that pixel rate of sink
decoding is not enough.

Taking 8bpp as an example, dsc clk needs to be 1/3 of the input
clk. the theoretical calculation of DEN compression 1/3, at this
time, the clk of vop dsc to hdmi tx can be reduced to about 260M
to meet the 8bpp transmission.

RK3588 dsc clk only supports 1/2 frequency division, so dsc clk
is 1/2 input clk, which needs to increase blank, which is
equivalent to compressing the absolute DEN time. TV is likely to
decode at a decoding rate of around 260M. DEN absolute time
shortening results in abnormal TV decoding.

So the value of hblank needs to be reduced when bpp is below 9.
The measurement can be displayed normally on TV, but reducing
the hblank will result in non-standard timing of the hdmi output.
This may cause compatibility issues and hdmi cts certification
may fail.

Change-Id: I48bebfab63742ef7e21913353c2771bdf947dc47
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>

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video/drm: vop2: calculate dclk divisions in Hz instead of KHz for RK3588

If MIPI0 is enabled and the &drm_display_mode.crtc_clock is 74250
in Khz that is equal with pixel clock rate, dclk_core_rate

video/drm: vop2: calculate dclk divisions in Hz instead of KHz for RK3588

If MIPI0 is enabled and the &drm_display_mode.crtc_clock is 74250
in Khz that is equal with pixel clock rate, dclk_core_rate will be
18562 in Khz, which is a quarter of pixel clock rate.

After the vop2_calc_dclk(), the final dclk rate will be four times
dclk_out_rate, which is the same as dclk_core_rate unless DSC mode
is enabled or the dual channel mode is configrated, is 74248 in KHz.
Then the dclk rate will be set to 74248000Hz unexpectly.

In conclusion, it will be more accurate to calculate dclk divisions
in Hz instead of KHz as the Kernel.

Change-Id: Ib31f5b18c739ca4044a3278cd940367805b9d4ee
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: enable the hdmitx compress mode configuration for RK3588 HDMI DSC mode

Change-Id: I3c811abe5ffa795b4fcc9b321a8c93f1a44e2122
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

video/drm: vop2: update the calculation of dclk_out division factor for RK3588 HDMI DSC mode

For RK3588, dclk_out is designed for DP, MIPI in both DSC and non-DSC
mode and HDMI in DSC mode.

In addd

video/drm: vop2: update the calculation of dclk_out division factor for RK3588 HDMI DSC mode

For RK3588, dclk_out is designed for DP, MIPI in both DSC and non-DSC
mode and HDMI in DSC mode.

In addditon, the dclk_out division factor should be the same as the
dclk_core division factor in HDMI DSC mode.

For the display interfaces that do not need the dclk_out, it should
be more appropriate to set dclk_out division factor to 0.

Change-Id: Idd254a105b5ea69caa25b315be8ff39a8c4fd10e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: fix the if_pixclk_div/if_dclk_div calculation for RK3588 HDMI DSC mode

The &crtc_state.dsc_cds_clk_rate is in Hz, but the dclk_rate is in
KHz. Divide &crtc_state.dsc_cds_clk_rate by

video/drm: vop2: fix the if_pixclk_div/if_dclk_div calculation for RK3588 HDMI DSC mode

The &crtc_state.dsc_cds_clk_rate is in Hz, but the dclk_rate is in
KHz. Divide &crtc_state.dsc_cds_clk_rate by 1000 to ensure the
accuracy of the clock division calculation.

Fixes: 12ee5af07a3 ("drm/rockchip: vop2: add support for dsc")
Change-Id: I012cd1f34304cf1b1c9fb2f4a99b26aeb69cbe2a
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: support to use the win scale to configure overscan parameters

For some platforms, such as RK3576, use the win scale instead
of the post scale to configure overscan parameters, becau

video/drm: vop2: support to use the win scale to configure overscan parameters

For some platforms, such as RK3576, use the win scale instead
of the post scale to configure overscan parameters, because the
sharp/post scale/split functions are mutually exclusice.

Change-Id: Iffb7d9eadca2ae9eefb71f14a91382e236f90e40
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: modify the check related to the cursor plane

In order to sync the cursor plane assignment with Kernel, the
modifications are as follows:
1.Change the type of &rockchip_vp.cursor_pla

video/drm: vop2: modify the check related to the cursor plane

In order to sync the cursor plane assignment with Kernel, the
modifications are as follows:
1.Change the type of &rockchip_vp.cursor_plane_id and
&vop2_vp_plane_mask.cursor_plane_id from int to u8.
2.Remove the unnecessary &vop2_data.plane_table.
3.Assign cursor plane according to the &vop2.possible_vp_mask and
&vop2_win_data.plane_type in the scenario where the cursor plane
specified in DTS is invalid.
4.Add cursor plane check in vop2_plane_mask_check().

Fixes: ee008497bf7 ("drm/rockchip: vop2: add adjust cursor plane")
Change-Id: I50e9a55d42f24131c50b351b2deb02bae1b003b2
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: check the hot plug capability for plane mask assignment only for RK3566

For RK3566, the main planes should be enabled before the mirror planes.
The devices that support hot plug may

video/drm: vop2: check the hot plug capability for plane mask assignment only for RK3566

For RK3566, the main planes should be enabled before the mirror planes.
The devices that support hot plug may be disconnected initially, so we
assign the main planes to the first device that does not support hot
plug, in order to ensure that the mirror planes are not enabled first.

For the platforms other than RK3566, we assign the plane mask of VPx
based on the &vop2_data.plane_mask[active_vp_num][x].

Change-Id: I7a5cc967623bf4aeb7d4bb9c5b0a36a288c30fc8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: modify the check related to the plane mask and primary plane

The check rule for plane mask that assigned in DTS is:

If plane_mask is assigned in DTS, then every plane need to be as

video/drm: vop2: modify the check related to the plane mask and primary plane

The check rule for plane mask that assigned in DTS is:

If plane_mask is assigned in DTS, then every plane need to be assigned
to one of all the VPs, and no single plane can be assigned to more than
one VP.

In order to check whether the plane mask and primary plane assigned in
DTS are valid, the modifications are as follows:
1.Move the process of automatically assigning the plane mask to a new
function vop2_plane_mask_assign(), which can also be called if the
plane mask and primary plane are invalid.
2.Add the &vop2_data.plane_mask_base for all platforms to help check
whether the plane mask assigned in DTS is valid.
3.Add the new function vop2_plane_mask_check() to check the plane mask
that assigned in DTS according to the above rule. If the return value
of vop2_plane_mask_check() is false, then automatically assign the
plane mask using the function vop2_plane_mask_assign().
4.Transfer valid plane mask that assigned in DTS to the
&vop2.possible_vp_mask. And the &vop2.possible_vp_mask is used in
vop2_win_can_attach_to_vp() to check whether the plane can attach to
the specific VP.
5.Remove &vop2_data.vp_default_primary_plane related codes, and Assign
default primary plane according to &vop2.possible_vp_mask and
&vop2_win_data.plane_type in the scenario where the plane mask is not
specified in DTS
6.Remove &vop2_data.vp_primary_plane_order, and add new function
vop2_vp_find_attachable_win() help select default primary plane when
the plane mask is assigned in DTS while the primary plane is not.
7.Skip rockchip_vop2_fixup_dts() for the VOP3 platforms in order not
to fixup the plane_mask related DTS properties when the plane mask
is not assigned in DTS.

Change-Id: I027d065b72768caa82b5bd979c5c3dba118ba567
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: config h-timing 2-pixel align for RK3576 DP

For RK3576 DP output, vp send 2 pixels 1 cycle. So the hactive,
hfp, hsync, hbp should be 2-pixel aligned.

Signed-off-by: Zhang Yubing <

video/drm: vop2: config h-timing 2-pixel align for RK3576 DP

For RK3576 DP output, vp send 2 pixels 1 cycle. So the hactive,
hfp, hsync, hbp should be 2-pixel aligned.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ie484e8f4e6bc7bb21910f151ff35b2c7fa7b9a6c

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drm/rockchip: vop2: use rkiommu 2.0 for vop axi0 by default

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ifa6b634901749f24e3b7afa8e3342348db7b1cea

video/drm: vop2: fix the unexpected logs related to the primary plane of the unused VPs

If only the logo display of VP0 is enabled in RK3576, the unexpected
logs may appear:
......
Assign plane mask

video/drm: vop2: fix the unexpected logs related to the primary plane of the unused VPs

If only the logo display of VP0 is enabled in RK3576, the unexpected
logs may appear:
......
Assign plane mask automatically
VOP have 1 active VP
vp0 have layer nr:1[Esmart0 ], primary plane: Esmart0
vp1 have layer nr:0[], primary plane: Cluster0
vp2 have layer nr:0[], primary plane: Cluster0
......

It is better to be like:
......
VOP have 1 active VP
vp0 have layer nr:1[Esmart0 ], primary plane: Esmart0
vp1 have layer nr:0[], primary plane: INVALID
vp2 have layer nr:0[], primary plane: INVALID
......

The modifications are:
1.Set primary plane id of unused VPs to ROCKCHIP_VOP2_PHY_ID_INVALID.
2.Convert the type of ROCKCHIP_VOP2_PHY_ID_INVALID to u8 to avoid
unexpected comparison result, due to the parameters
&vop2_vp_plane_mask.primary_plane_id and
&vop2_vp_plane_mask.attached_layers are also u8.

In addition, it may be better to rename vop2_plane_id_to_string() to
vop2_plane_phys_id_to_string() based on the definition of
&vop2_win_data.phys_id.

Change-Id: I4cea1d91fabc03d110d176282acab04670da9054
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: vop2: add &vop2_win_data.possible_vp_mask for all platforms

The &vop2_win_data.possible_vp_mask helps to check if the plane can
attach to the specific VP.

Change-Id: I67ef11085acc9272a14

video/drm: vop2: add &vop2_win_data.possible_vp_mask for all platforms

The &vop2_win_data.possible_vp_mask helps to check if the plane can
attach to the specific VP.

Change-Id: I67ef11085acc9272a147d6d187af74d0a7883ec7
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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