1*c5f8dd48SAndy Shevchenko /*
2*c5f8dd48SAndy Shevchenko * Copyright (c) 2017 Intel Corporation
3*c5f8dd48SAndy Shevchenko *
4*c5f8dd48SAndy Shevchenko * SPDX-License-Identifier: GPL-2.0+
5*c5f8dd48SAndy Shevchenko */
6*c5f8dd48SAndy Shevchenko
7*c5f8dd48SAndy Shevchenko #include <common.h>
8*c5f8dd48SAndy Shevchenko #include <dm.h>
9*c5f8dd48SAndy Shevchenko #include <ns16550.h>
10*c5f8dd48SAndy Shevchenko #include <serial.h>
11*c5f8dd48SAndy Shevchenko
12*c5f8dd48SAndy Shevchenko /*
13*c5f8dd48SAndy Shevchenko * The UART clock is calculated as
14*c5f8dd48SAndy Shevchenko *
15*c5f8dd48SAndy Shevchenko * UART clock = XTAL * UART_MUL / UART_DIV
16*c5f8dd48SAndy Shevchenko *
17*c5f8dd48SAndy Shevchenko * The baudrate is calculated as
18*c5f8dd48SAndy Shevchenko *
19*c5f8dd48SAndy Shevchenko * baud rate = UART clock / UART_PS / DLAB
20*c5f8dd48SAndy Shevchenko */
21*c5f8dd48SAndy Shevchenko #define UART_PS 0x30
22*c5f8dd48SAndy Shevchenko #define UART_MUL 0x34
23*c5f8dd48SAndy Shevchenko #define UART_DIV 0x38
24*c5f8dd48SAndy Shevchenko
mid_writel(struct ns16550_platdata * plat,int offset,int value)25*c5f8dd48SAndy Shevchenko static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
26*c5f8dd48SAndy Shevchenko {
27*c5f8dd48SAndy Shevchenko unsigned char *addr;
28*c5f8dd48SAndy Shevchenko
29*c5f8dd48SAndy Shevchenko offset *= 1 << plat->reg_shift;
30*c5f8dd48SAndy Shevchenko addr = (unsigned char *)plat->base + offset;
31*c5f8dd48SAndy Shevchenko
32*c5f8dd48SAndy Shevchenko writel(value, addr + plat->reg_offset);
33*c5f8dd48SAndy Shevchenko }
34*c5f8dd48SAndy Shevchenko
mid_serial_probe(struct udevice * dev)35*c5f8dd48SAndy Shevchenko static int mid_serial_probe(struct udevice *dev)
36*c5f8dd48SAndy Shevchenko {
37*c5f8dd48SAndy Shevchenko struct ns16550_platdata *plat = dev_get_platdata(dev);
38*c5f8dd48SAndy Shevchenko
39*c5f8dd48SAndy Shevchenko /*
40*c5f8dd48SAndy Shevchenko * Initialize fractional divider correctly for Intel Edison
41*c5f8dd48SAndy Shevchenko * platform.
42*c5f8dd48SAndy Shevchenko *
43*c5f8dd48SAndy Shevchenko * For backward compatibility we have to set initial DLAB value
44*c5f8dd48SAndy Shevchenko * to 16 and speed to 115200 baud, where initial frequency is
45*c5f8dd48SAndy Shevchenko * 29491200Hz, and XTAL frequency is 38.4MHz.
46*c5f8dd48SAndy Shevchenko */
47*c5f8dd48SAndy Shevchenko mid_writel(plat, UART_MUL, 96);
48*c5f8dd48SAndy Shevchenko mid_writel(plat, UART_DIV, 125);
49*c5f8dd48SAndy Shevchenko mid_writel(plat, UART_PS, 16);
50*c5f8dd48SAndy Shevchenko
51*c5f8dd48SAndy Shevchenko return ns16550_serial_probe(dev);
52*c5f8dd48SAndy Shevchenko }
53*c5f8dd48SAndy Shevchenko
54*c5f8dd48SAndy Shevchenko static const struct udevice_id mid_serial_ids[] = {
55*c5f8dd48SAndy Shevchenko { .compatible = "intel,mid-uart" },
56*c5f8dd48SAndy Shevchenko {}
57*c5f8dd48SAndy Shevchenko };
58*c5f8dd48SAndy Shevchenko
59*c5f8dd48SAndy Shevchenko U_BOOT_DRIVER(serial_intel_mid) = {
60*c5f8dd48SAndy Shevchenko .name = "serial_intel_mid",
61*c5f8dd48SAndy Shevchenko .id = UCLASS_SERIAL,
62*c5f8dd48SAndy Shevchenko .of_match = mid_serial_ids,
63*c5f8dd48SAndy Shevchenko .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
64*c5f8dd48SAndy Shevchenko .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
65*c5f8dd48SAndy Shevchenko .priv_auto_alloc_size = sizeof(struct NS16550),
66*c5f8dd48SAndy Shevchenko .probe = mid_serial_probe,
67*c5f8dd48SAndy Shevchenko .ops = &ns16550_serial_ops,
68*c5f8dd48SAndy Shevchenko .flags = DM_FLAG_PRE_RELOC,
69*c5f8dd48SAndy Shevchenko };
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