irq: use commmon name for read and write operation

It maybe i2c and spi interface, etc.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I320dd67289f42e75515ae247f67d12cc4167347c

Merge branch 'next-dev' into thunder-boot

irq: virq: add parent irq enable/disable management

- disable virq chip by default;
- fix bank->use_count little than 0;

Change-Id: I69aa07cc2924dab40eea6524588869361ad8cf66
Signed-off-by: Joseph C

irq: virq: add parent irq enable/disable management

- disable virq chip by default;
- fix bank->use_count little than 0;

Change-Id: I69aa07cc2924dab40eea6524588869361ad8cf66
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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irq: add irq_handler_enable_suspend_only() interface

Change-Id: I3cda4c3a4ce5928be32eaa8b65ccd4e16946c116
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: add virq irq-chip support

This patch support the device to add its interrupt controller as "irq chip"
into generic interrupt framework, the other driver can request its child
interrupt like a r

irq: add virq irq-chip support

This patch support the device to add its interrupt controller as "irq chip"
into generic interrupt framework, the other driver can request its child
interrupt like a real hardware irq.

Example for PMIC:
GIC-\
|- ...
|- GPIO-\
|- ...
|- PMIC-\
|_ virq_0
|_ virq_1
|_ virq_2
|...
|_ virq_n

Change-Id: I17716f3db494a85fc22b23ff18042771a6116da8
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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irq: clean up code

Change-Id: I51c2713b7c42fa798fee6971a2c91d867042ef70
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: clean up code

- using IRQ_X() to print message;
- update some comment;
- rename some function;
- add more strict irq sanity;

Change-Id: If5432818d4bc12fc1aa0b8aca6898bbf79dfa9fb
Signed-off-by:

irq: clean up code

- using IRQ_X() to print message;
- update some comment;
- rename some function;
- add more strict irq sanity;

Change-Id: If5432818d4bc12fc1aa0b8aca6898bbf79dfa9fb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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irq: add irq busy validation

return -EBUSY when this irq is occupied.

Change-Id: I75ad6c0b13e167762cab2b8f9a2b786e588b2ade
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq; support irq revert trigger type and get gpio level

Change-Id: Ib897bb37c518429c595903bb8f2cfd9fcea9aa78
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: support irq suspend and resume

U-Boot will support cpu suspend/resume, cpu and logic may
lose power, this patch guarantees gic works normally.

Change-Id: I8ebee881fa27fea075502f962f9faabaa8264

irq: support irq suspend and resume

U-Boot will support cpu suspend/resume, cpu and logic may
lose power, this patch guarantees gic works normally.

Change-Id: I8ebee881fa27fea075502f962f9faabaa8264f67
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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drivers: irq: support convert gpio to irq by gpio fdt phandle

add funtion: phandle_gpio_to_irq(u32 gpio_phandle, u32 pin)

Change-Id: Iec2d1ed08138c2476bb13deb16ca06960fadd60d
Signed-off-by: Joseph

drivers: irq: support convert gpio to irq by gpio fdt phandle

add funtion: phandle_gpio_to_irq(u32 gpio_phandle, u32 pin)

Change-Id: Iec2d1ed08138c2476bb13deb16ca06960fadd60d
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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drivers: irq: deliver both irq and private data to irq handler

gic irq handler only need private data, while gpio irq(parent bank)
handler needs private data and irq number for getting gpio bank and

drivers: irq: deliver both irq and private data to irq handler

gic irq handler only need private data, while gpio irq(parent bank)
handler needs private data and irq number for getting gpio bank and
pin information. So we need deliver both of them to the irq handler.

This patch fixes the legacy code issue.

Change-Id: I1917b588a867e807cbd15e2e4101ae259cf4a40f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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drivers: add irq interrupt framework support

This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.

The framework support gic i

drivers: add irq interrupt framework support

This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.

The framework support gic interrupt and gpio interrupt, relative APIs
are provided in: ./include/irq-platform.h

If you'd like to add a new platform support into interrupt framework,
please follow the steps:
1. add relative definitions in the file like other platforms:
./include/irq-platform.h

2. add GICD, GICC and GICR(for GICV3) base address definitions in the
rkxxx-common.h, they are needed in: arch/arm/cpu/armv8/start.S;

3. enable CONFIG_GICV2 or CONFIG_GICV3.

Notice:
1. the framework is initialize in function 'interrupt_init()' of
_sequence_r[]. So you should not request irqs too early.

2. IRQ stack size is configured by CONFIG_IRQ_STACK_SIZE, the default
value is 8KB when CONFIG_IRQ_STACK_SIZE is absent.

Change-Id: I3d9e29873c9d64cd28aabd13a61111438c5902b0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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