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Searched refs:ref_clk (Results 1 – 25 of 26) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_combtxphy.c293 unsigned long ref_clk; in rk628_combtxphy_set_mode() local
305 ref_clk = rk628_cru_clk_get_rate(rk628, CGU_SCLK_VOP); in rk628_combtxphy_set_mode()
306 ref_clk = DIV_ROUND_CLOSEST(ref_clk, 1000); /* khz */ in rk628_combtxphy_set_mode()
309 ref_clk /= 2; in rk628_combtxphy_set_mode()
315 best_delta_freq = ref_clk; in rk628_combtxphy_set_mode()
317 fpfd = ref_clk / i; in rk628_combtxphy_set_mode()
329 do_div(pre_clk, ref_clk); in rk628_combtxphy_set_mode()
335 bus_width = ref_clk / combtxphy->ref_div * 8; in rk628_combtxphy_set_mode()
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dspi-zynq-qspi.txt10 - clock-names : List of input clock names - "ref_clk", "pclk"
20 clock-names = "ref_clk", "pclk";
H A Dspi-zynq.txt10 - clock-names : List of input clock names - "ref_clk", "pclk"
25 clock-names = "ref_clk", "pclk";
H A Dspi-cadence.txt18 - tshsl-ns : Added delay in master reference clocks (ref_clk) for
21 - tsd2d-ns : Delay in master reference clocks (ref_clk) between one
/rk3399_rockchip-uboot/board/beckhoff/mx53cx9020/
H A Dmx53cx9020.c237 u32 ref_clk = MXC_HCLK; in clock_1GHz() local
242 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); in clock_1GHz()
246 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in clock_1GHz()
247 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in clock_1GHz()
/rk3399_rockchip-uboot/board/aries/m53evk/
H A Dm53evk.c314 const uint32_t ref_clk = MXC_HCLK; in m53_set_clock() local
325 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); in m53_set_clock()
329 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); in m53_set_clock()
335 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); in m53_set_clock()
/rk3399_rockchip-uboot/board/freescale/mx53loco/
H A Dmx53loco.c347 u32 ref_clk = MXC_HCLK; in clock_1GHz() local
352 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); in clock_1GHz()
356 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); in clock_1GHz()
357 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); in clock_1GHz()
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_mipi.h15 u32 ref_clk; member
H A Drk3399_mipi.c86 priv->ref_clk = 24 * MHz; in rk_display_enable()
87 priv->sys_clk = priv->ref_clk; in rk_display_enable()
H A Drk3288_mipi.c94 priv->ref_clk = 24 * MHz; in rk_mipi_enable()
95 priv->sys_clk = priv->ref_clk; in rk_mipi_enable()
H A Drk_mipi.c208 u32 refclk = priv->ref_clk; in rk_mipi_phy_enable()
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c87 struct clk ref_clk; member
288 ret = clk_enable(&priv->ref_clk); in rockchip_combphy_init()
304 clk_disable(&priv->ref_clk); in rockchip_combphy_init()
318 clk_disable(&priv->ref_clk); in rockchip_combphy_exit()
364 ret = clk_get_by_index(dev, 0, &priv->ref_clk); in rockchip_combphy_parse_dt()
367 return PTR_ERR(&priv->ref_clk); in rockchip_combphy_parse_dt()
566 clk_set_rate(&priv->ref_clk, 100000000); in rk3562_combphy_cfg()
864 clk_set_rate(&priv->ref_clk, 100000000); in rk3588_combphy_cfg()
1002 clk_set_rate(&priv->ref_clk, 100000000); in rk3576_combphy_cfg()
1119 clk_set_rate(&priv->ref_clk, 100000000); in rv1126b_combphy_cfg()
/rk3399_rockchip-uboot/board/inversepath/usbarmory/
H A Dusbarmory.c370 u32 ref_clk = MXC_HCLK; in set_clock() local
375 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); in set_clock()
379 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); in set_clock()
384 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); in set_clock()
/rk3399_rockchip-uboot/drivers/spi/
H A Dcadence_qspi.h74 unsigned int ref_clk, unsigned int sclk_hz,
H A Dcadence_qspi_apb.c336 unsigned int ref_clk, unsigned int sclk_hz, in cadence_qspi_apb_delay() argument
348 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk); in cadence_qspi_apb_delay()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dzynq-7000.dtsi187 clock-names = "ref_clk", "pclk";
199 clock-names = "ref_clk", "pclk";
205 clock-names = "ref_clk", "pclk";
322 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
H A Dzynqmp.dtsi706 clock-names = "ref_clk", "pclk";
833 clock-names = "ref_clk", "pclk";
845 clock-names = "ref_clk", "pclk";
918 clock-names = "bus_clk", "ref_clk";
941 clock-names = "bus_clk", "ref_clk";
H A Dr8a7795-h3ulcb.dts262 clock-names = "clk_in", "ref_clk";
H A Dr8a7795-salvator-x.dts396 clock-names = "clk_in", "ref_clk";
H A Drk3399.dtsi388 clock-names = "ref_clk", "suspend_clk",
422 clock-names = "ref_clk", "suspend_clk",
H A Drk3328.dtsi644 clock-names = "ref_clk", "suspend_clk",
H A Drk3568.dtsi258 clock-names = "ref_clk", "suspend_clk",
290 clock-names = "ref_clk", "suspend_clk",
H A Drk1808.dtsi101 clock-names = "ref_clk", "bus_clk",
H A Drv1126.dtsi1996 clock-names = "ref_clk", "bus_clk", "hclk";
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c68 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) argument
69 #define PLL_FREQ_MIN(ref_clk) \ argument
70 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)

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