xref: /rk3399_rockchip-uboot/drivers/video/drm/rk628/rk628_combtxphy.c (revision 48b136cf33e9398c6e5fa53498ee84471b43d6d3)

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd
 *
 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
 */

#include <config.h>
#include <common.h>
#include <errno.h>
#include <dm.h>
#include <div64.h>
#include <asm/io.h>
#include <linux/ioport.h>
#include <linux/iopoll.h>
#include <linux/math64.h>

#include "rk628.h"
#include "rk628_cru.h"
#include "rk628_combtxphy.h"

static void rk628_combtxphy_dsi_power_on(struct rk628 *rk628)
{
	struct rk628_combtxphy *combtxphy = &rk628->combtxphy;
	u32 val = 0;
	int ret;

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_BUS_WIDTH_MASK |
			      SW_GVI_LVDS_EN_MASK | SW_MIPI_DSI_EN_MASK,
			       SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN);

	if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
				      SW_MODULEA_EN_MASK, SW_MODULEA_EN);

	if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
				      SW_MODULEB_EN_MASK, SW_MODULEB_EN);

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL, SW_PD_PLL);

	if (combtxphy->frac_div)
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON8, SW_SSC_DEPTH_MASK | SW_SSC_EN_MASK,
				      SW_SSC_DEPTH(0) | SW_SSC_EN(1));

	rk628_i2c_write(rk628, COMBTXPHY_CON5,
			SW_REF_DIV(combtxphy->ref_div - 1) |
			SW_PLL_FB_DIV(combtxphy->fb_div) |
			SW_PLL_FRAC_DIV(combtxphy->frac_div) |
			SW_RATE(combtxphy->rate_div / 2));

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL, 0);

	ret = rk628_read_poll_timeout(rk628, GRF_DPHY0_STATUS, val,
				       val & DPHY_PHYLOCK, 0, 1000);
	if (ret < 0)
		printf("rk628 phy is not lock\n");

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON9,
			SW_DSI_FSET_EN_MASK | SW_DSI_RCAL_EN_MASK,
			SW_DSI_FSET_EN | SW_DSI_RCAL_EN(1));

	if (rk628->version == RK628F_VERSION) {
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON6,
				      SW_PLL_CTL_CON0_MASK,
				      SW_PLL_CTL_CON0(1));
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON9,
				      SW_DSI_LPTX_SR_TRIM_MASK |
				      SW_DSI_HSTX_AMP_TRIM_MASK,
				      SW_DSI_LPTX_SR_TRIM(0) |
				      SW_DSI_HSTX_AMP_TRIM(4));
	}

	udelay(400);
}

static void rk628_combtxphy_lvds_power_on(struct rk628 *rk628)
{

	struct rk628_combtxphy *combtxphy = &rk628->combtxphy;
	u32 val;
	int ret;

	/* Adjust terminal resistance 133 ohm, bypass 0.95v ldo for driver. */
	if (rk628->version == RK628F_VERSION)
		val = TX_COM_VOLT_ADJ(3);
	else
		val = TX_COM_VOLT_ADJ(0);
	rk628_i2c_update_bits(rk628, COMBTXPHY_CON7,
			      SW_TX_RTERM_MASK | SW_TX_MODE_MASK |
			      BYPASS_095V_LDO_MASK | TX_COM_VOLT_ADJ_MASK,
			      SW_TX_RTERM(6) | SW_TX_MODE(3) |
			      BYPASS_095V_LDO(1) | val);

	rk628_i2c_write(rk628, COMBTXPHY_CON10, TX7_CKDRV_EN | TX2_CKDRV_EN);
	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
			      SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
			      SW_MIPI_DSI_EN_MASK,
			      SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN);

	if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
				      SW_MODULEA_EN_MASK, SW_MODULEA_EN);

	if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
		rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
				      SW_MODULEB_EN_MASK, SW_MODULEB_EN);

	rk628_i2c_write(rk628, COMBTXPHY_CON5,
			SW_REF_DIV(combtxphy->ref_div - 1) |
			SW_PLL_FB_DIV(combtxphy->fb_div) |
			SW_PLL_FRAC_DIV(combtxphy->frac_div) |
			SW_RATE(combtxphy->rate_div / 2));

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
			      SW_PD_PLL, 0);

	ret = rk628_read_poll_timeout(rk628, GRF_DPHY0_STATUS, val,
				       val & DPHY_PHYLOCK, 0, 1000);
	if (ret < 0)
		printf("rk628 phy is not lock\n");

	udelay(200);
	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_TX_IDLE_MASK | SW_TX_PD_MASK, 0);
}

static void rk628_combtxphy_gvi_power_on(struct rk628 *rk628)
{
	struct rk628_combtxphy *combtxphy = &rk628->combtxphy;
	int ref_div = 0;

	if (combtxphy->ref_div % 2) {
		ref_div = combtxphy->ref_div - 1;
	} else {
		ref_div = BIT(4);
		ref_div |= combtxphy->ref_div / 2 - 1;
	}

	rk628_i2c_write(rk628, COMBTXPHY_CON5,
			SW_REF_DIV(ref_div) |
			SW_PLL_FB_DIV(combtxphy->fb_div) |
			SW_PLL_FRAC_DIV(combtxphy->frac_div) |
			SW_RATE(combtxphy->rate_div / 2));
	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
			      SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
			      SW_MIPI_DSI_EN_MASK |
			      SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
			      SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN |
			      SW_MODULEB_EN | SW_MODULEA_EN);

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
			      SW_PD_PLL | SW_TX_PD_MASK, 0);
	udelay(200);
	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
			      SW_TX_IDLE_MASK, 0);
}

void rk628_combtxphy_power_on(struct rk628 *rk628)
{
	struct rk628_combtxphy *combtxphy = &rk628->combtxphy;

	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0,
			      SW_TX_IDLE_MASK | SW_TX_PD_MASK |
			      SW_PD_PLL_MASK, SW_TX_IDLE(0x3ff) |
			      SW_TX_PD(0x3ff) | SW_PD_PLL);

	switch (combtxphy->mode) {
	case RK628_PHY_MODE_VIDEO_MIPI:

		rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON,
				      SW_TXPHY_REFCLK_SEL_MASK,
				      SW_TXPHY_REFCLK_SEL(0));
		rk628_combtxphy_dsi_power_on(rk628);
		break;
	case RK628_PHY_MODE_VIDEO_LVDS:
		rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON,
				      SW_TXPHY_REFCLK_SEL_MASK,
				      SW_TXPHY_REFCLK_SEL(1));
		rk628_combtxphy_lvds_power_on(rk628);
		break;
	case RK628_PHY_MODE_VIDEO_GVI:
		rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON,
				      SW_TXPHY_REFCLK_SEL_MASK,
				      SW_TXPHY_REFCLK_SEL(2));
		rk628_combtxphy_gvi_power_on(rk628);
		break;
	default:
		break;
	};
}

void rk628_combtxphy_power_off(struct rk628 *rk628)
{
	rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_TX_IDLE_MASK |
			      SW_TX_PD_MASK | SW_PD_PLL_MASK |
			      SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
			      SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
}

void rk628_combtxphy_set_bus_width(struct rk628 *rk628, u32 bus_width)
{
	rk628->combtxphy.bus_width = bus_width;
}

u32 rk628_combtxphy_get_bus_width(struct rk628 *rk628)
{
	return rk628->combtxphy.bus_width;
}

void rk628_combtxphy_set_gvi_division_mode(struct rk628 *rk628, bool division)
{
	rk628->combtxphy.division_mode = division;
}

void rk628_combtxphy_set_mode(struct rk628 *rk628, enum rk628_phy_mode mode)
{
	struct rk628_combtxphy *combtxphy = &rk628->combtxphy;
	unsigned int fvco, fpfd, fin = 24;

	switch (mode) {
	case RK628_PHY_MODE_VIDEO_MIPI:
	{
		int bus_width = rk628_combtxphy_get_bus_width(rk628);
		unsigned int fhsc = bus_width >> 8;
		unsigned int flags = bus_width & 0xff;

		combtxphy->flags = flags;

		/*
		 * the VCO can work from 1.5GHz to 3GHz.
		 * fhsc: 80 ~ 374, fvco: 640 ~ 2992
		 * fhsc: 375 ~ 749, fvco: 1500 ~ 2996
		 * fhsc: 750 ~ 1500, fvco: 1500 ~ 3000
		 */
		if (fhsc < 80 || fhsc > 1500)
			return;
		else if (fhsc < 375)
			combtxphy->rate_div = 4;
		else if (fhsc < 750)
			combtxphy->rate_div = 2;
		else
			combtxphy->rate_div = 1;

		fvco = fhsc * 2 * combtxphy->rate_div;

		/*
		 * the reference clock at PFD(FPFD = ref_clk / ref_div) about
		 * 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
		 * here to find the best ref_div.
		 */
		combtxphy->ref_div = 1;

		/*
		 * fvco = fin * (fb_div + frac_div / 1024) * 8 / ref_div
		 */
		combtxphy->fb_div = fvco * combtxphy->ref_div / 8 / fin;
		combtxphy->frac_div = 1024 * fvco * combtxphy->ref_div / 8 / fin;
		combtxphy->frac_div -= 1024 * combtxphy->fb_div;

		/*
		 * get the actually frequency
		 */
		fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div) * 8;
		fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div);
		fhsc = fvco / 2 / combtxphy->rate_div;
		combtxphy->bus_width = fhsc;

		break;
	}
	case RK628_PHY_MODE_VIDEO_LVDS:
	{
		int bus_width = rk628_combtxphy_get_bus_width(rk628);
		unsigned int flags = bus_width & 0xff;
		unsigned int rate = (bus_width >> 8) * 7;

		combtxphy->flags = flags;
		combtxphy->ref_div = 1;
		combtxphy->fb_div = 14;
		combtxphy->frac_div = 0;

		if (rate < 500)
			combtxphy->rate_div = 4;
		else if (rate < 1000)
			combtxphy->rate_div = 2;
		else
			combtxphy->rate_div = 1;
		break;
	}
	case RK628_PHY_MODE_VIDEO_GVI:
	{
		unsigned int i, delta_freq, best_delta_freq, fb_div;
		unsigned int bus_width = rk628_combtxphy_get_bus_width(rk628);
		unsigned long ref_clk;
		unsigned long long pre_clk;

		if (bus_width < 500000 || bus_width > 4000000)
			return;
		else if (bus_width < 1000000)
			combtxphy->rate_div = 4;
		else if (bus_width < 2000000)
			combtxphy->rate_div = 2;
		else
			combtxphy->rate_div = 1;
		fvco = bus_width * combtxphy->rate_div;
		ref_clk = rk628_cru_clk_get_rate(rk628, CGU_SCLK_VOP);
		ref_clk = DIV_ROUND_CLOSEST(ref_clk, 1000); /* khz */

		if (combtxphy->division_mode)
			ref_clk /= 2;
		/*
		 * the reference clock at PFD(FPFD = ref_clk / ref_div) about
		 * 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
		 * here to find the best rev_div.
		 */
		best_delta_freq = ref_clk;
		for (i = 1; i <= 32; i++) {
			fpfd = ref_clk / i;
			delta_freq = abs(fpfd - 25000);
			if (delta_freq < best_delta_freq) {
				best_delta_freq = delta_freq;
				combtxphy->ref_div = i;
			}
		}

		/*
		 * ref_clk / ref_div * 8 * fb_div = FVCO
		 */
		pre_clk = (unsigned long long)fvco * combtxphy->ref_div / 8 * 1024;
		do_div(pre_clk, ref_clk);
		fb_div = pre_clk / 1024;

		/*
		 * get the actually frequency
		 */
		bus_width = ref_clk / combtxphy->ref_div * 8;
		bus_width *= fb_div;
		bus_width /= combtxphy->rate_div;

		combtxphy->frac_div = 0;
		combtxphy->fb_div = fb_div;

		combtxphy->bus_width = bus_width;
		break;
	}
	default:
		break;
	}

	combtxphy->mode = mode;
}