1*8097cba8SVikas ManochaCadence QSPI controller device tree bindings 2*8097cba8SVikas Manocha-------------------------------------------- 3*8097cba8SVikas Manocha 4*8097cba8SVikas ManochaRequired properties: 5*8097cba8SVikas Manocha- compatible : should be "cadence,qspi". 6*8097cba8SVikas Manocha- reg : 1.Physical base address and size of SPI registers map. 7*8097cba8SVikas Manocha 2. Physical base address & size of NOR Flash. 8*8097cba8SVikas Manocha- clocks : Clock phandles (see clock bindings for details). 9*8097cba8SVikas Manocha- sram-size : spi controller sram size. 10*8097cba8SVikas Manocha- status : enable in requried dts. 11*8097cba8SVikas Manocha 12*8097cba8SVikas Manochaconnected flash properties 13*8097cba8SVikas Manocha-------------------------- 14*8097cba8SVikas Manocha 15*8097cba8SVikas Manocha- spi-max-frequency : Max supported spi frequency. 16*8097cba8SVikas Manocha- page-size : Flash page size. 17*8097cba8SVikas Manocha- block-size : Flash memory block size. 18*8097cba8SVikas Manocha- tshsl-ns : Added delay in master reference clocks (ref_clk) for 19*8097cba8SVikas Manocha the length that the master mode chip select outputs 20*8097cba8SVikas Manocha are de-asserted between transactions. 21*8097cba8SVikas Manocha- tsd2d-ns : Delay in master reference clocks (ref_clk) between one 22*8097cba8SVikas Manocha chip select being de-activated and the activation of 23*8097cba8SVikas Manocha another. 24*8097cba8SVikas Manocha- tchsh-ns : Delay in master reference clocks between last bit of 25*8097cba8SVikas Manocha current transaction and de-asserting the device chip 26*8097cba8SVikas Manocha select (n_ss_out). 27*8097cba8SVikas Manocha- tslch-ns : Delay in master reference clocks between setting 28*8097cba8SVikas Manocha n_ss_out low and first bit transfer 29