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Searched refs:pll_div (Results 1 – 14 of 14) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dcpu.c116 static unsigned pll_div(volatile void *pllbase, unsigned offset) in pll_div() function
131 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
133 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
141 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
144 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
168 return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); in pll_sysclk_mhz()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3368.c31 struct pll_div { struct
48 static struct pll_div rk3368_pll_rates[] = { argument
113 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
114 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
116 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
117 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
129 struct pll_div *rkclk_get_pll_config(ulong freq_hz) in rkclk_get_pll_config()
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
143 struct pll_div *best_div = NULL; in pll_para_config()
250 const struct pll_div *div) in rkclk_set_pll()
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H A Dclk_rk3399.c35 struct pll_div { struct
54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); argument
56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1);
57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1);
58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
59 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
60 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
62 static const struct pll_div *apll_cfgs[] = {
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) in rkclk_set_pll()
445 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config()
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H A Dclk_rk3066.c55 struct pll_div { struct
103 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
104 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
108 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
144 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
190 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
H A Dclk_rk3188.c56 struct pll_div { struct
101 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
102 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
106 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
142 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
188 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
H A Dclk_rk3288.c34 struct pll_div { struct
51 static struct pll_div rk3288_pll_rates[] = { argument
219 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
220 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4);
221 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
223 struct pll_div *rkclk_get_pll_config(ulong freq_hz) in rkclk_get_pll_config()
236 const struct pll_div *div) in rkclk_set_pll()
305 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
355 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
357 struct pll_div *best_div = NULL; in pll_para_config()
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H A Dclk_rk3036.c59 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
60 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
63 const struct pll_div *div) in rkclk_set_pll()
H A Dclk_rv1108.c40 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
41 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
66 const struct pll_div *div) in rkclk_set_pll()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/
H A Dclock.c776 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
783 pll_div, pll_num, pll_denom); in enable_pll_video()
797 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
803 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
809 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
815 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
822 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
899 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
943 pll_div = best / hck; in mxs_set_lcdclk()
945 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
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/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dclock.c552 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
559 pll_div, pll_num, pll_denom); in enable_pll_video()
571 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
576 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
581 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
627 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
698 pll_div = best / hck; in mxs_set_lcdclk()
700 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
711 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
748 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rv1108.h55 struct pll_div dpll_init_cfg;
H A Dcru_rk3036.h66 struct pll_div { struct
H A Dcru_rv1108.h54 struct pll_div { struct
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c40 const struct pll_div dpll_init_cfg = {1, 100, 3, 1};