34 struct pll_div {  struct
51 static struct pll_div rk3288_pll_rates[] = {  argument
219 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
220 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4);
221 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
223 struct pll_div *rkclk_get_pll_config(ulong freq_hz)  in rkclk_get_pll_config()
236 			 const struct pll_div *div)  in rkclk_set_pll()
305 	static const struct pll_div dpll_cfg[] = {  in rkclk_configure_ddr()
355 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)  in pll_para_config()
357 	struct pll_div *best_div = NULL;  in pll_para_config()
477 	struct pll_div cpll_config = {0};  in rockchip_vop_set_clk()