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Searched refs:phydev (Results 1 – 25 of 131) sorted by relevance

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/rk3399_rockchip-uboot/drivers/net/phy/
H A Dbroadcom.c38 static void bcm_phy_write_misc(struct phy_device *phydev, in bcm_phy_write_misc() argument
43 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
46 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
48 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
53 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
57 static int bcm5461_config(struct phy_device *phydev) in bcm5461_config() argument
59 genphy_config_aneg(phydev); in bcm5461_config()
61 phy_reset(phydev); in bcm5461_config()
66 static int bcm54xx_parse_status(struct phy_device *phydev) in bcm54xx_parse_status() argument
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H A Dmarvell.c108 static int m88e1011s_config(struct phy_device *phydev) in m88e1011s_config() argument
111 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
121 genphy_config_aneg(phydev); in m88e1011s_config()
129 static int m88e1xxx_parse_status(struct phy_device *phydev) in m88e1xxx_parse_status() argument
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H A Datheros.c20 static int ar8021_config(struct phy_device *phydev) in ar8021_config() argument
22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
25 phydev->supported = phydev->drv->features; in ar8021_config()
29 static int ar8031_config(struct phy_device *phydev) in ar8031_config() argument
31 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in ar8031_config()
32 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { in ar8031_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
39 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || in ar8031_config()
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H A Drealtek.c54 static int rtl8211b_probe(struct phy_device *phydev) in rtl8211b_probe() argument
57 phydev->flags |= PHY_RTL8211x_FORCE_MASTER; in rtl8211b_probe()
64 static int rtl8211x_config(struct phy_device *phydev) in rtl8211x_config() argument
66 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
71 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
74 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { in rtl8211x_config()
77 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
82 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
85 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); in rtl8211x_config()
87 genphy_config_aneg(phydev); in rtl8211x_config()
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H A Dphy.c38 static int genphy_config_advert(struct phy_device *phydev) in genphy_config_advert() argument
45 phydev->advertising &= phydev->supported; in genphy_config_advert()
46 advertise = phydev->advertising; in genphy_config_advert()
49 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
75 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); in genphy_config_advert()
82 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
94 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
102 if (phydev->supported & (SUPPORTED_1000baseT_Half | in genphy_config_advert()
113 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
128 static int genphy_setup_forced(struct phy_device *phydev) in genphy_setup_forced() argument
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H A Drk630phy.c122 static int rk630_phy_startup(struct phy_device *phydev) in rk630_phy_startup() argument
127 ret = genphy_update_link(phydev); in rk630_phy_startup()
132 phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in rk630_phy_startup()
134 return genphy_parse_link(phydev); in rk630_phy_startup()
137 static void rk630_phy_s40_config_init(struct phy_device *phydev) in rk630_phy_s40_config_init() argument
139 phy_write(phydev, 0, MDIO_DEVAD_NONE, in rk630_phy_s40_config_init()
140 phy_read(phydev, MDIO_DEVAD_NONE, 0) & ~BIT(13)); in rk630_phy_s40_config_init()
143 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0100); in rk630_phy_s40_config_init()
145 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE1_APS_CTRL, 0x4824); in rk630_phy_s40_config_init()
147 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0200); in rk630_phy_s40_config_init()
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H A Dmicrel_ksz90x1.c45 static int ksz90xx_startup(struct phy_device *phydev) in ksz90xx_startup() argument
50 ret = genphy_update_link(phydev); in ksz90xx_startup()
54 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
57 phydev->duplex = DUPLEX_FULL; in ksz90xx_startup()
59 phydev->duplex = DUPLEX_HALF; in ksz90xx_startup()
62 phydev->speed = SPEED_1000; in ksz90xx_startup()
64 phydev->speed = SPEED_100; in ksz90xx_startup()
66 phydev->speed = SPEED_10; in ksz90xx_startup()
109 static int ksz90x1_of_config_group(struct phy_device *phydev, in ksz90x1_of_config_group() argument
112 struct udevice *dev = phydev->dev; in ksz90x1_of_config_group()
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H A Dvitesse.c70 static int vitesse_config(struct phy_device *phydev) in vitesse_config() argument
73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
79 genphy_config_aneg(phydev); in vitesse_config()
84 static int vitesse_parse_status(struct phy_device *phydev) in vitesse_parse_status() argument
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
92 phydev->duplex = DUPLEX_FULL; in vitesse_parse_status()
94 phydev->duplex = DUPLEX_HALF; in vitesse_parse_status()
99 phydev->speed = SPEED_1000; in vitesse_parse_status()
102 phydev->speed = SPEED_100; in vitesse_parse_status()
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H A Dmv88e61xx.c217 __weak int mv88e61xx_hw_reset(struct phy_device *phydev) in mv88e61xx_hw_reset() argument
256 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) in mv88e61xx_reg_read() argument
258 struct mv88e61xx_phy_priv *priv = phydev->priv; in mv88e61xx_reg_read()
292 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, in mv88e61xx_reg_write() argument
295 struct mv88e61xx_phy_priv *priv = phydev->priv; in mv88e61xx_reg_write()
331 static int mv88e61xx_phy_wait(struct phy_device *phydev) in mv88e61xx_phy_wait() argument
337 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
351 struct phy_device *phydev; in mv88e61xx_phy_read_indirect() local
354 phydev = (struct phy_device *)smi_wrapper->priv; in mv88e61xx_phy_read_indirect()
357 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_read_indirect()
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H A Dnatsemi.c18 static int dp83630_config(struct phy_device *phydev) in dp83630_config() argument
22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
31 genphy_config_aneg(phydev); in dp83630_config()
56 static int dp838xx_config(struct phy_device *phydev) in dp838xx_config() argument
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
59 genphy_config_aneg(phydev); in dp838xx_config()
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H A Dmscc.c137 static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev) in mscc_vsc8531_vsc8541_init_scripts() argument
142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
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H A Dti.c116 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, in phy_read_mmd_indirect() argument
122 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_read_mmd_indirect()
125 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_read_mmd_indirect()
128 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_read_mmd_indirect()
131 value = phy_read(phydev, addr, MII_MMD_DATA); in phy_read_mmd_indirect()
151 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, in phy_write_mmd_indirect() argument
155 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_write_mmd_indirect()
158 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_write_mmd_indirect()
161 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_write_mmd_indirect()
164 phy_write(phydev, addr, MII_MMD_DATA, data); in phy_write_mmd_indirect()
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H A Daquantia.c22 int aquantia_config(struct phy_device *phydev) in aquantia_config() argument
24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
26 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in aquantia_config()
28 phydev->advertising = SUPPORTED_1000baseT_Full; in aquantia_config()
29 phydev->supported = phydev->advertising; in aquantia_config()
32 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
33 } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) { in aquantia_config()
35 phydev->advertising = SUPPORTED_10000baseT_Full; in aquantia_config()
36 phydev->supported = phydev->advertising; in aquantia_config()
40 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
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H A Dxilinx_phy.c36 static int xilinxphy_startup(struct phy_device *phydev) in xilinxphy_startup() argument
45 err = genphy_update_link(phydev); in xilinxphy_startup()
49 if (AUTONEG_ENABLE == phydev->autoneg) { in xilinxphy_startup()
50 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in xilinxphy_startup()
54 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup()
56 phydev->duplex = DUPLEX_HALF; in xilinxphy_startup()
60 phydev->speed = SPEED_1000; in xilinxphy_startup()
64 phydev->speed = SPEED_100; in xilinxphy_startup()
68 phydev->speed = SPEED_10; in xilinxphy_startup()
72 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
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H A Dgeneric_10g.c17 int gen10g_shutdown(struct phy_device *phydev) in gen10g_shutdown() argument
22 int gen10g_startup(struct phy_device *phydev) in gen10g_startup() argument
25 u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; in gen10g_startup()
27 phydev->link = 1; in gen10g_startup()
30 phydev->speed = SPEED_10000; in gen10g_startup()
31 phydev->duplex = DUPLEX_FULL; in gen10g_startup()
43 phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
44 reg = phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
46 phydev->link = 0; in gen10g_startup()
52 int gen10g_discover_mmds(struct phy_device *phydev) in gen10g_discover_mmds() argument
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H A Dmicrel_ksz8xxx.c33 static int ksz_genconfig_bcastoff(struct phy_device *phydev) in ksz_genconfig_bcastoff() argument
37 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
41 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, in ksz_genconfig_bcastoff()
46 return genphy_config(phydev); in ksz_genconfig_bcastoff()
65 static int ksz8051_config(struct phy_device *phydev) in ksz8051_config() argument
70 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
72 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); in ksz8051_config()
74 return genphy_config(phydev); in ksz8051_config()
111 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) in ksz8895_write_smireg() argument
113 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, in ksz8895_write_smireg()
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H A Ddavicom.c27 static int dm9161_config(struct phy_device *phydev) in dm9161_config() argument
29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
31 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
37 genphy_config_aneg(phydev); in dm9161_config()
42 static int dm9161_parse_status(struct phy_device *phydev) in dm9161_parse_status() argument
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
49 phydev->speed = SPEED_100; in dm9161_parse_status()
51 phydev->speed = SPEED_10; in dm9161_parse_status()
54 phydev->duplex = DUPLEX_FULL; in dm9161_parse_status()
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H A Dteranetics.c17 int tn2020_config(struct phy_device *phydev) in tn2020_config() argument
19 if (phydev->port == PORT_FIBRE) { in tn2020_config()
31 phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; in tn2020_config()
33 phy_write(phydev, 30, 93, 2); in tn2020_config()
34 phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); in tn2020_config()
36 phy_write(phydev, 30, 93, 1); in tn2020_config()
43 int tn2020_startup(struct phy_device *phydev) in tn2020_startup() argument
58 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); in tn2020_startup()
61 "address %u\n", phydev->addr); in tn2020_startup()
74 "align.\n", phydev->addr); in tn2020_startup()
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H A Det1011c.c28 static int et1011c_config(struct phy_device *phydev) in et1011c_config() argument
31 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
39 return genphy_config_aneg(phydev); in et1011c_config()
42 static int et1011c_parse_status(struct phy_device *phydev) in et1011c_parse_status() argument
47 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
50 phydev->duplex = DUPLEX_FULL; in et1011c_parse_status()
52 phydev->duplex = DUPLEX_HALF; in et1011c_parse_status()
57 phydev->speed = SPEED_1000; in et1011c_parse_status()
58 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
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H A Dlxt.c21 static int lxt971_parse_status(struct phy_device *phydev) in lxt971_parse_status() argument
26 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2); in lxt971_parse_status()
31 phydev->speed = SPEED_10; in lxt971_parse_status()
32 phydev->duplex = DUPLEX_HALF; in lxt971_parse_status()
35 phydev->speed = SPEED_10; in lxt971_parse_status()
36 phydev->duplex = DUPLEX_FULL; in lxt971_parse_status()
39 phydev->speed = SPEED_100; in lxt971_parse_status()
40 phydev->duplex = DUPLEX_HALF; in lxt971_parse_status()
43 phydev->speed = SPEED_100; in lxt971_parse_status()
44 phydev->duplex = DUPLEX_FULL; in lxt971_parse_status()
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H A Drockchip-fephy.c63 static int rockchip_fephy_group_read(struct phy_device *phydev, u8 group, u32 reg) in rockchip_fephy_group_read() argument
67 ret = phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_CFGCNTL, CFGCNTL_READ(group, reg)); in rockchip_fephy_group_read()
72 return phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD1); in rockchip_fephy_group_read()
74 return (phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD1) | in rockchip_fephy_group_read()
75 (phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD2) << 16)); in rockchip_fephy_group_read()
78 static int rockchip_fephy_group_write(struct phy_device *phydev, u8 group, in rockchip_fephy_group_write() argument
83 ret = phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTWRITE, val); in rockchip_fephy_group_write()
87 return phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_CFGCNTL, CFGCNTL_WRITE(group, reg)); in rockchip_fephy_group_write()
90 static int rockchip_fephy_startup(struct phy_device *phydev) in rockchip_fephy_startup() argument
95 ret = genphy_update_link(phydev); in rockchip_fephy_startup()
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H A Dfixed.c17 int fixedphy_probe(struct phy_device *phydev) in fixedphy_probe() argument
20 int ofnode = phydev->addr; in fixedphy_probe()
36 phydev->priv = priv; in fixedphy_probe()
44 phydev->flags |= PHY_FLAG_BROKEN_RESET; in fixedphy_probe()
49 int fixedphy_startup(struct phy_device *phydev) in fixedphy_startup() argument
51 struct fixed_link *priv = phydev->priv; in fixedphy_startup()
53 phydev->asym_pause = priv->asym_pause; in fixedphy_startup()
54 phydev->pause = priv->pause; in fixedphy_startup()
55 phydev->duplex = priv->duplex; in fixedphy_startup()
56 phydev->speed = priv->link_speed; in fixedphy_startup()
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/rk3399_rockchip-uboot/include/
H A Dphy.h90 int (*probe)(struct phy_device *phydev);
94 int (*config)(struct phy_device *phydev);
97 int (*startup)(struct phy_device *phydev);
100 int (*shutdown)(struct phy_device *phydev);
102 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
103 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
107 int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
110 int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
162 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) in phy_read() argument
164 struct mii_dev *bus = phydev->bus; in phy_read()
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/rk3399_rockchip-uboot/board/spear/x600/
H A Dx600.c72 int board_phy_config(struct phy_device *phydev) in board_phy_config() argument
77 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
78 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
84 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
87 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
92 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
97 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
102 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
114 phy_reset(phydev); in board_phy_config()
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/rk3399_rockchip-uboot/board/keymile/kmp204x/
H A Deth.c56 int board_phy_config(struct phy_device *phydev) in board_phy_config() argument
58 if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) { in board_phy_config()
60 if (phydev->drv->config) in board_phy_config()
61 phydev->drv->config(phydev); in board_phy_config()
64 phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); in board_phy_config()
65 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); in board_phy_config()
66 phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); in board_phy_config()

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