Lines Matching refs:phydev
70 static int vitesse_config(struct phy_device *phydev) in vitesse_config() argument
73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
79 genphy_config_aneg(phydev); in vitesse_config()
84 static int vitesse_parse_status(struct phy_device *phydev) in vitesse_parse_status() argument
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
92 phydev->duplex = DUPLEX_FULL; in vitesse_parse_status()
94 phydev->duplex = DUPLEX_HALF; in vitesse_parse_status()
99 phydev->speed = SPEED_1000; in vitesse_parse_status()
102 phydev->speed = SPEED_100; in vitesse_parse_status()
105 phydev->speed = SPEED_10; in vitesse_parse_status()
112 static int vitesse_startup(struct phy_device *phydev) in vitesse_startup() argument
116 ret = genphy_update_link(phydev); in vitesse_startup()
119 return vitesse_parse_status(phydev); in vitesse_startup()
122 static int cis8204_config(struct phy_device *phydev) in cis8204_config() argument
125 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
128 genphy_config_aneg(phydev); in cis8204_config()
130 if (phy_interface_is_rgmii(phydev)) in cis8204_config()
131 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
135 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
145 static int vsc8601_add_skew(struct phy_device *phydev) in vsc8601_add_skew() argument
149 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
154 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
157 static int vsc8601_config(struct phy_device *phydev) in vsc8601_config() argument
161 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc8601_config()
162 ret = vsc8601_add_skew(phydev); in vsc8601_config()
167 return genphy_config_aneg(phydev); in vsc8601_config()
170 static int vsc8574_config(struct phy_device *phydev) in vsc8574_config() argument
174 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
177 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
178 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8574_config()
181 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8574_config()
184 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, in vsc8574_config()
189 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val); in vsc8574_config()
191 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, in vsc8574_config()
194 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
197 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
200 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
202 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON); in vsc8574_config()
204 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val); in vsc8574_config()
206 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); in vsc8574_config()
208 genphy_config_aneg(phydev); in vsc8574_config()
213 static int vsc8514_config(struct phy_device *phydev) in vsc8514_config() argument
219 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8514_config()
222 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); in vsc8514_config()
223 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8514_config()
226 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8514_config()
229 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18, in vsc8514_config()
237 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
240 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
247 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); in vsc8514_config()
250 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); in vsc8514_config()
253 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val); in vsc8514_config()
256 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8514_config()
258 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON); in vsc8514_config()
260 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val); in vsc8514_config()
261 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); in vsc8514_config()
263 genphy_config_aneg(phydev); in vsc8514_config()
268 static int vsc8664_config(struct phy_device *phydev) in vsc8664_config() argument
273 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); in vsc8664_config()
274 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON); in vsc8664_config()
276 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val); in vsc8664_config()
278 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8664_config()
280 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET); in vsc8664_config()
282 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val); in vsc8664_config()
283 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); in vsc8664_config()
286 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON); in vsc8664_config()
288 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val); in vsc8664_config()
290 genphy_config_aneg(phydev); in vsc8664_config()