63 static int rockchip_fephy_group_read(struct phy_device *phydev, u8 group, u32 reg)  in rockchip_fephy_group_read()  argument
67 	ret = phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_CFGCNTL, CFGCNTL_READ(group, reg));  in rockchip_fephy_group_read()
72 		return phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD1);  in rockchip_fephy_group_read()
74 		return (phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD1) |  in rockchip_fephy_group_read()
75 			(phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD2) << 16));  in rockchip_fephy_group_read()
78 static int rockchip_fephy_group_write(struct phy_device *phydev, u8 group,  in rockchip_fephy_group_write()  argument
83 	ret = phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTWRITE, val);  in rockchip_fephy_group_write()
87 	return phy_write(phydev, MDIO_DEVAD_NONE, SMI_ADDR_CFGCNTL, CFGCNTL_WRITE(group, reg));  in rockchip_fephy_group_write()
90 static int rockchip_fephy_startup(struct phy_device *phydev)  in rockchip_fephy_startup()  argument
95 	ret = genphy_update_link(phydev);  in rockchip_fephy_startup()
100 	phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);  in rockchip_fephy_startup()
102 	return genphy_parse_link(phydev);  in rockchip_fephy_startup()
105 static int rockchip_fephy_config_init(struct phy_device *phydev)  in rockchip_fephy_config_init()  argument
110 	ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_LED_CTRL, 0x7aa);  in rockchip_fephy_config_init()
115 	ret = rockchip_fephy_group_write(phydev, GROUP_CFG0, 0xa, 0x6664);  in rockchip_fephy_config_init()
120 	ret = rockchip_fephy_group_write(phydev, GROUP_CFG0, 0x18, 0xc);  in rockchip_fephy_config_init()
129 		sel = rockchip_fephy_group_read(phydev, GROUP_AFE, 0x3);  in rockchip_fephy_config_init()
132 		ret = rockchip_fephy_group_write(phydev, GROUP_AFE, 0x3, sel | 0x2);  in rockchip_fephy_config_init()
137 		ret = rockchip_fephy_group_write(phydev, GROUP_CFG0, 0x1a, 0x6);  in rockchip_fephy_config_init()