Lines Matching refs:phydev
137 static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev) in mscc_vsc8531_vsc8541_init_scripts() argument
142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
174 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
177 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
182 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
183 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
188 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
189 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
193 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in mscc_vsc8531_vsc8541_init_scripts()
199 static int mscc_parse_status(struct phy_device *phydev) in mscc_parse_status() argument
204 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG); in mscc_parse_status()
207 phydev->duplex = DUPLEX_FULL; in mscc_parse_status()
209 phydev->duplex = DUPLEX_HALF; in mscc_parse_status()
216 phydev->speed = SPEED_1000; in mscc_parse_status()
219 phydev->speed = SPEED_100; in mscc_parse_status()
222 phydev->speed = SPEED_10; in mscc_parse_status()
225 phydev->speed = SPEED_10; in mscc_parse_status()
232 static int mscc_startup(struct phy_device *phydev) in mscc_startup() argument
236 retval = genphy_update_link(phydev); in mscc_startup()
241 return mscc_parse_status(phydev); in mscc_startup()
244 static int mscc_phy_soft_reset(struct phy_device *phydev) in mscc_phy_soft_reset() argument
250 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in mscc_phy_soft_reset()
253 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
254 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); in mscc_phy_soft_reset()
256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
259 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
266 phydev->interface); in mscc_phy_soft_reset()
273 static int vsc8531_vsc8541_mac_config(struct phy_device *phydev) in vsc8531_vsc8541_mac_config() argument
282 switch (phydev->interface) { in vsc8531_vsc8541_mac_config()
307 phydev->interface); in vsc8531_vsc8541_mac_config()
311 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8531_vsc8541_mac_config()
314 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
320 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
323 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
326 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
331 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
334 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8531_vsc8541_mac_config()
340 static int vsc8531_config(struct phy_device *phydev) in vsc8531_config() argument
350 mscc_vsc8531_vsc8541_init_scripts(phydev); in vsc8531_config()
353 switch (phydev->interface) { in vsc8531_config()
356 retval = vsc8531_vsc8541_mac_config(phydev); in vsc8531_config()
360 retval = mscc_phy_soft_reset(phydev); in vsc8531_config()
366 phydev->interface); in vsc8531_config()
372 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8531_config()
374 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG); in vsc8531_config()
383 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val); in vsc8531_config()
385 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL); in vsc8531_config()
393 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc8531_config()
394 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8531_config()
397 return genphy_config_aneg(phydev); in vsc8531_config()
400 static int vsc8541_config(struct phy_device *phydev) in vsc8541_config() argument
410 mscc_vsc8531_vsc8541_init_scripts(phydev); in vsc8541_config()
413 switch (phydev->interface) { in vsc8541_config()
418 retval = vsc8531_vsc8541_mac_config(phydev); in vsc8541_config()
422 retval = mscc_phy_soft_reset(phydev); in vsc8541_config()
428 phydev->interface); in vsc8541_config()
434 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8541_config()
436 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG); in vsc8541_config()
443 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val); in vsc8541_config()
445 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL); in vsc8541_config()
453 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc8541_config()
454 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8541_config()
457 return genphy_config_aneg(phydev); in vsc8541_config()