| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rv1126b.c | 828 u32 reg, reg_h, src, con, p_rate; in rv1126b_frac_get_rate() local
888 p_rate = OSC_HZ; in rv1126b_frac_get_rate()
891 p_rate = priv->gpll_hz; in rv1126b_frac_get_rate()
894 p_rate = priv->aupll_hz; in rv1126b_frac_get_rate()
897 p_rate = priv->cpll_hz; in rv1126b_frac_get_rate()
913 return p_rate * n / m; in rv1126b_frac_get_rate()
920 u32 src, p_rate, val; in rv1126b_frac_set_rate() local
925 p_rate = OSC_HZ; in rv1126b_frac_set_rate()
928 p_rate = priv->aupll_hz; in rv1126b_frac_set_rate()
931 p_rate = priv->cpll_hz; in rv1126b_frac_set_rate()
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| H A D | clk_rk3576.c | 1561 u32 con, div, src, p_rate; in rk3576_gmac_get_clk() local
1570 p_rate = priv->gpll_hz; in rk3576_gmac_get_clk()
1572 p_rate = priv->cpll_hz; in rk3576_gmac_get_clk()
1574 p_rate = GMAC0_PTP_REFCLK_IN; in rk3576_gmac_get_clk()
1575 return DIV_TO_RATE(p_rate, div); in rk3576_gmac_get_clk()
1582 p_rate = priv->gpll_hz; in rk3576_gmac_get_clk()
1584 p_rate = priv->cpll_hz; in rk3576_gmac_get_clk()
1586 p_rate = GMAC1_PTP_REFCLK_IN; in rk3576_gmac_get_clk()
1587 return DIV_TO_RATE(p_rate, div); in rk3576_gmac_get_clk()
1665 u32 reg, con, fracdiv, p_src, p_rate; in rk3576_uart_frac_get_rate() local
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| H A D | clk_rk3568.c | 2095 u32 con, div, p_rate; in rk3568_ebc_get_clk() local
2099 p_rate = DIV_TO_RATE(priv->cpll_hz, div); in rk3568_ebc_get_clk()
2107 return p_rate; in rk3568_ebc_get_clk()
2135 u32 con, div, src, p_rate; in rk3568_rkvdec_get_clk() local
2144 p_rate = priv->cpll_hz; in rk3568_rkvdec_get_clk()
2146 p_rate = priv->gpll_hz; in rk3568_rkvdec_get_clk()
2147 return DIV_TO_RATE(p_rate, div); in rk3568_rkvdec_get_clk()
2155 p_rate = priv->cpll_hz; in rk3568_rkvdec_get_clk()
2157 p_rate = priv->npll_hz; in rk3568_rkvdec_get_clk()
2159 p_rate = priv->vpll_hz; in rk3568_rkvdec_get_clk()
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| H A D | clk_rv1106.c | 808 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rv1106_uart_get_rate() local
839 p_rate = priv->gpll_hz; in rv1106_uart_get_rate()
841 p_rate = priv->cpll_hz; in rv1106_uart_get_rate()
843 p_rate = 480000000; in rv1106_uart_get_rate()
845 return DIV_TO_RATE(p_rate, div); in rv1106_uart_get_rate()
852 return DIV_TO_RATE(p_rate, div) * n / m; in rv1106_uart_get_rate()
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| H A D | clk_pll.c | 375 ulong rate, p_rate = OSC_HZ / KHZ; in rk3036_pll_get_rate() local
407 rate = (p_rate * fbdiv / (refdiv * postdiv1 * postdiv2)) * KHZ; in rk3036_pll_get_rate()
409 u64 frac_rate = p_rate * (u64)frac * KHZ; in rk3036_pll_get_rate()
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| H A D | clk_rv1103b.c | 661 u32 reg, con, fracdiv, div, src, p_rate; in rv1103b_uart_get_rate() local
690 p_rate = priv->gpll_hz; in rv1103b_uart_get_rate()
692 return DIV_TO_RATE(p_rate, div); in rv1103b_uart_get_rate()
699 return DIV_TO_RATE(p_rate, div) * n / m; in rv1103b_uart_get_rate()
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| H A D | clk_rk3328.c | 387 u32 div, con, mux, p_rate; in rk3328_spi_get_clk() local
393 p_rate = priv->gpll_hz; in rk3328_spi_get_clk()
395 p_rate = priv->cpll_hz; in rk3328_spi_get_clk()
397 return DIV_TO_RATE(p_rate, div); in rk3328_spi_get_clk()
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| H A D | clk_rk3128.c | 515 uint p_rate; in rk3128_crypto_set_rate() local
517 p_rate = rk3128_bus_get_clk(priv, ACLK_CPU); in rk3128_crypto_set_rate()
518 src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1; in rk3128_crypto_set_rate()
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| H A D | clk_rk3562.c | 447 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3562_uart_get_rate() local
504 p_rate = priv->gpll_hz; in rk3562_uart_get_rate()
506 p_rate = priv->cpll_hz; in rk3562_uart_get_rate()
508 return DIV_TO_RATE(p_rate, div); in rk3562_uart_get_rate()
515 return DIV_TO_RATE(p_rate, div) * n / m; in rk3562_uart_get_rate()
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| H A D | clk_rk3368.c | 853 uint p_rate; in rk3368_crypto_set_rate() local
855 p_rate = rk3368_bus_get_clk(priv->cru, ACLK_BUS); in rk3368_crypto_set_rate()
856 src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1; in rk3368_crypto_set_rate()
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| H A D | clk_rk3288.c | 1011 uint p_rate; in rockchip_crypto_set_clk() local
1013 p_rate = rockchip_aclk_cpu_get_clk(cru); in rockchip_crypto_set_clk()
1014 src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1; in rockchip_crypto_set_clk()
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| H A D | clk_rk3588.c | 1325 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3588_uart_get_rate() local
1365 p_rate = priv->gpll_hz; in rk3588_uart_get_rate()
1367 p_rate = priv->cpll_hz; in rk3588_uart_get_rate()
1370 return DIV_TO_RATE(p_rate, div); in rk3588_uart_get_rate()
1377 return DIV_TO_RATE(p_rate, div) * n / m; in rk3588_uart_get_rate()
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