| /rk3399_rockchip-uboot/include/linux/ |
| H A D | log2.h | 27 int __ilog2_u32(u32 n) in __ilog2_u32() argument
29 return fls(n) - 1; in __ilog2_u32()
35 int __ilog2_u64(u64 n) in __ilog2_u64() argument
37 return fls64(n) - 1; in __ilog2_u64()
50 bool is_power_of_2(unsigned long n) in is_power_of_2() argument
52 return (n != 0 && ((n & (n - 1)) == 0)); in is_power_of_2()
60 unsigned long __roundup_pow_of_two(unsigned long n) in __roundup_pow_of_two() argument
62 return 1UL << fls_long(n - 1); in __roundup_pow_of_two()
70 unsigned long __rounddown_pow_of_two(unsigned long n) in __rounddown_pow_of_two() argument
72 return 1UL << (fls_long(n) - 1); in __rounddown_pow_of_two()
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| /rk3399_rockchip-uboot/tools/omap/ |
| H A D | clocks_get_m_n.c | 54 u32 m, n; in get_m_n_optimized() local
55 n = 1; in get_m_n_optimized()
57 m = target_freq_khz / ref_freq_khz / 2 * n; in get_m_n_optimized()
60 freq = ref_freq_khz * 2 * m / n; in get_m_n_optimized()
72 n_optimal = n; in get_m_n_optimized()
74 n++; in get_m_n_optimized()
76 ((ref_freq_khz / n) < 1000)) { in get_m_n_optimized()
80 n--; in get_m_n_optimized()
90 u32 m, n; in main() local
92 get_m_n_optimized(2000000, 12000, &m, &n); in main()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | prcm.h | 16 #define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) argument
18 #define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) argument
19 #define PRCM_CPUS_CFG_PRE_DIV(n) \ argument
20 __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
21 #define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) argument
23 #define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) argument
24 #define PRCM_CPUS_CFG_POST_DIV(n) \ argument
25 __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
26 #define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) argument
41 #define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) argument
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| H A D | p2wi.h | 25 #define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) argument
27 #define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) argument
28 #define P2WI_CC_CLK_DIV(n) \ argument
29 __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
30 #define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) argument
40 #define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) argument
67 #define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) argument
69 #define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) argument
71 #define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) argument
73 #define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) argument
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| H A D | dram_sun4i.h | 108 #define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) argument
112 #define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) argument
120 #define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) argument
125 #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) argument
128 #define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) argument
137 #define DRAM_DRR_TRFC(n) ((n) & 0xff) argument
138 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) argument
139 #define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) argument
141 #define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) argument
143 #define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) argument
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| H A D | clock_sun4i.h | 186 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) argument
213 #define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) argument
217 #define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) argument
219 #define CCM_PLL5_CTRL_M_X(n) ((n) - 1) argument
220 #define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) argument
222 #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) argument
223 #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) argument
226 #define CCM_PLL5_CTRL_K_X(n) ((n) - 1) argument
228 #define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) argument
231 #define CCM_PLL5_CTRL_N_X(n) (n) argument
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| H A D | lcdc.h | 79 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) argument
81 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) argument
83 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) argument
84 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) argument
85 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) argument
86 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) argument
92 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) argument
95 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) argument
98 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) argument
99 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) argument
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| H A D | dram_sun9i.h | 183 #define MCTL_INIT0_POST_CKE_x1024(n) ((n & 0x0fff) << 16) argument
188 #define MCTL_INIT0_PRE_CKE_x1024(n) ((n & 0x0fff) << 0) argument
189 #define MCTL_INIT1_DRAM_RSTN_x1024(n) ((n & 0xff) << 16) argument
190 #define MCTL_INIT1_FINAL_WAIT_x32(n) ((n & 0x3f) << 8) argument
191 #define MCTL_INIT1_PRE_OCD_x32(n) ((n & 0x0f) << 0) argument
192 #define MCTL_INIT2_IDLE_AFTER_RESET_x32(n) ((n & 0xff) << 8) argument
193 #define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n) ((n & 0x0f) << 0) argument
194 #define MCTL_INIT3_MR(n) ((n & 0xffff) << 16) argument
195 #define MCTL_INIT3_EMR(n) ((n & 0xffff) << 0) argument
196 #define MCTL_INIT4_EMR2(n) ((n & 0xffff) << 16) argument
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| H A D | clock_sun6i.h | 199 #define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) argument
200 #define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) argument
201 #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) argument
202 #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) argument
207 #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) argument
210 #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) argument
215 #define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) argument
216 #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) argument
217 #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) argument
234 #define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) argument
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_common.h | 30 #define UART_INFO_ID(n) (((n) >> 28) & 0xf) argument
31 #define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf) argument
32 #define UART_INFO_BAUD(n) ((n) & 0xffffff) argument
35 #define STANDBY_IDLE(n) ((n) & 0xffff) argument
37 #define SR_INFO(n) (((n) >> 16) & 0xffff) argument
38 #define PD_INFO(n) ((n) & 0xffff) argument
40 #define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf) argument
41 #define CHANNEL_MASK(n) (((n) >> 24) & 0xf) argument
42 #define STRIDE_TYPE(n) (((n) >> 16) & 0xff) argument
44 #define DDR_2T_INFO(n) ((n) & 1) argument
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| H A D | sdram_px30.h | 19 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) argument
22 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
24 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
42 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
43 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) argument
44 #define FBDIV(n) ((0xFFF << 16) | (n)) argument
47 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
48 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) argument
49 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) argument
50 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) argument
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| H A D | sdram_rk3328.h | 34 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
36 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
39 #define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15)) argument
40 #define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14)) argument
41 #define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13)) argument
42 #define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12)) argument
43 #define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11)) argument
44 #define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9)) argument
45 #define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8)) argument
46 #define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7)) argument
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| H A D | sdram_rv1126.h | 181 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) argument
187 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
189 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
206 #define UPCTL2_ASRSTN_REQ(n) (((0x1 << 0) << 16) | ((n) << 0)) argument
207 #define UPCTL2_PSRSTN_REQ(n) (((0x1 << 1) << 16) | ((n) << 1)) argument
208 #define UPCTL2_SRSTN_REQ(n) (((0x1 << 2) << 16) | ((n) << 2)) argument
212 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
213 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) argument
214 #define FBDIV(n) ((0xFFF << 16) | (n)) argument
217 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
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| H A D | dram_spec_timing.h | 88 #define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ argument
89 | ((((n) - 4) & 0x8) >> 1))
90 #define DDR3_WR(n) (((n) & 0x7) << 9) argument
97 #define DDR3_MR1_AL(n) (((n) & 0x3) << 3) argument
110 #define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) argument
137 #define LPDDR2_N_WR(n) (((n) - 2) << 5) argument
212 #define LPDDR3_N_WR(n) ((n) << 5) argument
399 #define DDR4_WR_RTP(n) ((n) << 9) argument
400 #define DDR4_CL(n) ((((n) & 0xe) << 3) | ((n) & 1) << 2) argument
401 #define DDR4_DLL_RESET(n) ((n) << 8) argument
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | timer.h | 29 #define TIMER_IR_CR(n) (1 << ((n) + 4)) argument
30 #define TIMER_IR_MR(n) (1 << (n)) argument
38 #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) argument
39 #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) argument
40 #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) argument
43 #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) argument
44 #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) argument
45 #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) argument
48 #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) argument
49 #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) argument
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| H A D | uart.h | 56 #define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) argument
91 #define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) argument
93 #define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) argument
94 #define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) argument
95 #define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) argument
96 #define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) argument
99 #define UART_LOOPBACK(n) (1 << ((n) - 1)) argument
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| /rk3399_rockchip-uboot/drivers/usb/dwc3/ |
| H A D | core.h | 102 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) argument
103 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) argument
105 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) argument
107 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) argument
109 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) argument
110 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) argument
112 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) argument
113 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) argument
114 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) argument
115 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) argument
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| H A D | gadget.h | 31 #define DWC3_DEPCFG_INT_NUM(n) ((n) << 0) argument
37 #define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16) argument
39 #define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25) argument
44 #define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1) argument
45 #define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3) argument
46 #define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17) argument
47 #define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22) argument
48 #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) argument
57 #define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) argument
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| /rk3399_rockchip-uboot/include/ |
| H A D | fm_eth.h | 67 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ argument
71 .num = n - 1, \
73 .port = FM##idx##_DTSEC##n, \
74 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
75 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
77 offsetof(struct ccsr_fman, memac[n-1]),\
81 #define FM_TGEC_INFO_INITIALIZER(idx, n) \ argument
85 .num = n - 1, \
87 .port = FM##idx##_10GEC##n, \
88 .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
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| H A D | fsl_ifc.h | 73 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ argument
74 (__ilog2(n) - IFC_AMASK_SHIFT))
115 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) argument
139 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) argument
168 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) argument
176 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) argument
180 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) argument
199 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) argument
201 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) argument
203 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) argument
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| /rk3399_rockchip-uboot/arch/arm/include/asm/ti-common/ |
| H A D | davinci_nand.h | 77 #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) argument
79 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) argument
80 #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) argument
88 #define DAVINCI_ABCR_WSETUP(n) (n << 26) argument
89 #define DAVINCI_ABCR_WSTROBE(n) (n << 20) argument
90 #define DAVINCI_ABCR_WHOLD(n) (n << 17) argument
91 #define DAVINCI_ABCR_RSETUP(n) (n << 13) argument
92 #define DAVINCI_ABCR_RSTROBE(n) (n << 7) argument
93 #define DAVINCI_ABCR_RHOLD(n) (n << 4) argument
94 #define DAVINCI_ABCR_TA(n) (n << 2) argument
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| /rk3399_rockchip-uboot/drivers/gpio/ |
| H A D | mxs_gpio.c | 18 #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) argument
19 #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) argument
20 #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10)) argument
21 #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) argument
22 #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) argument
23 #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) argument
26 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) argument
27 #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) argument
28 #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10)) argument
29 #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10)) argument
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| /rk3399_rockchip-uboot/tools/ |
| H A D | getline.c | 22 static int getstr(char **lineptr, size_t *n, FILE *stream, in getstr() argument
29 if (!lineptr || !n || !stream) in getstr()
33 *n = MIN_CHUNK; in getstr()
34 *lineptr = malloc(*n); in getstr()
39 nchars_avail = *n - offset; in getstr()
49 assert(*n - nchars_avail == read_pos - *lineptr); in getstr()
51 if (*n > MIN_CHUNK) in getstr()
52 *n *= 2; in getstr()
54 *n += MIN_CHUNK; in getstr()
56 nchars_avail = *n + *lineptr - read_pos; in getstr()
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| /rk3399_rockchip-uboot/board/Synology/ds414/ |
| H A D | cmd_syno.c | 37 int ret, n; in do_syno_populate() local
59 for (n = 0; n < ETHADDR_MAX; n++) { in do_syno_populate()
64 for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) { in do_syno_populate()
72 printf("Invalid MAC address for interface %d!\n", n); in do_syno_populate()
75 if (n == 0) in do_syno_populate()
78 sprintf(var, "eth%daddr", n); in do_syno_populate()
92 for (n = 0; bufp[n] && bufp[n] != ','; n++) in do_syno_populate()
93 csum += bufp[n]; in do_syno_populate()
94 bufp[n] = '\0'; in do_syno_populate()
97 bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG); in do_syno_populate()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/ |
| H A D | cpu.c | 56 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
57 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
58 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
59 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
74 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
75 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
76 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
77 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
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