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Searched refs:clk_src (Results 1 – 16 of 16) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c837 unsigned int clk_src, divisor, nocclk, src_hz; in cm_get_noc_clk_hz() local
840 clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) & in cm_get_noc_clk_hz()
845 if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) { in cm_get_noc_clk_hz()
850 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) { in cm_get_noc_clk_hz()
857 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) { in cm_get_noc_clk_hz()
859 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) { in cm_get_noc_clk_hz()
861 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) { in cm_get_noc_clk_hz()
912 u32 clk_src, mainmpuclk_reg; in cm_get_mpu_clk_hz() local
916 clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) & in cm_get_mpu_clk_hz()
921 switch (clk_src) { in cm_get_mpu_clk_hz()
[all …]
/rk3399_rockchip-uboot/drivers/spi/
H A Dmxc_spi.c96 u32 clk_src; in spi_cfg_mxc() local
101 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc()
103 div = DIV_ROUND_UP(clk_src, max_hz); in spi_cfg_mxc()
107 max_hz, div, clk_src / (4 << div)); in spi_cfg_mxc()
133 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc() local
151 if (clk_src > max_hz) { in spi_cfg_mxc()
152 pre_div = (clk_src - 1) / max_hz; in spi_cfg_mxc()
/rk3399_rockchip-uboot/board/freescale/s32v234evb/
H A Dclock.c20 u32 clk_src; in select_pll_source_clk() local
27 clk_src = SRC_GPR1_FIRC_CLK_SOURCE; in select_pll_source_clk()
30 clk_src = SRC_GPR1_XOSC_CLK_SOURCE; in select_pll_source_clk()
54 writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src), in select_pll_source_clk()
/rk3399_rockchip-uboot/drivers/mmc/
H A Dmeson_gx_mmc.c36 unsigned int clk, clk_src, clk_div; in meson_mmc_config_clock() local
41 clk_src = CLK_SRC_DIV2; in meson_mmc_config_clock()
44 clk_src = CLK_SRC_24M; in meson_mmc_config_clock()
55 meson_mmc_clk |= clk_src; in meson_mmc_config_clock()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c797 u32 clk_src; in config_ddr_clk() local
807 clk_src = get_periph_clk(); in config_ddr_clk()
827 if ((clk_src % emi_clk) < 10000000) in config_ddr_clk()
828 div = clk_src / emi_clk; in config_ddr_clk()
830 div = (clk_src / emi_clk) + 1; in config_ddr_clk()
/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy.h88 bool clk_src; member
H A Dcomphy_core.c165 comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, in comphy_probe()
H A Dcomphy_cp110.c87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, in comphy_pcie_power_up() argument
130 if (pcie_clk && clk_src && (lane == 5)) { in comphy_pcie_power_up()
2000 lane, pcie_width, ptr_comphy_map->clk_src, in comphy_cp110_init()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3576.c1704 u32 reg, clk_src, p_rate; in rk3576_uart_frac_set_rate() local
1708 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3576_uart_frac_set_rate()
1711 clk_src = CLK_UART_SRC_SEL_OSC; in rk3576_uart_frac_set_rate()
1714 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3576_uart_frac_set_rate()
1751 (clk_src << CLK_UART_SRC_SEL_SHIFT)); in rk3576_uart_frac_set_rate()
1839 u32 reg, clk_src = 0, div = 0; in rk3576_uart_set_rate() local
1842 clk_src = CLK_UART_SEL_GPLL; in rk3576_uart_set_rate()
1845 clk_src = CLK_UART_SEL_CPLL; in rk3576_uart_set_rate()
1848 clk_src = CLK_UART_SEL_FRAC0; in rk3576_uart_set_rate()
1851 clk_src = CLK_UART_SEL_FRAC1; in rk3576_uart_set_rate()
[all …]
H A Dclk_rk3588.c1387 u32 reg, clk_src, uart_src, div; in rk3588_uart_set_rate() local
1391 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1395 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3588_uart_set_rate()
1399 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1403 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1446 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3588_uart_set_rate()
1497 u32 clk_src, div; in rk3588_pciephy_set_rate() local
1500 clk_src = CLK_PCIE_PHY_REF_SEL_24M; in rk3588_pciephy_set_rate()
1503 clk_src = CLK_PCIE_PHY_REF_SEL_PPLL; in rk3588_pciephy_set_rate()
1511 (clk_src << CLK_PCIE_PHY0_REF_SEL_SHIFT)); in rk3588_pciephy_set_rate()
[all …]
H A Dclk_rk3568.c2283 u32 reg, clk_src, uart_src, div; in rk3568_uart_set_rate() local
2287 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2291 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3568_uart_set_rate()
2295 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2299 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2342 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3568_uart_set_rate()
2429 u32 reg, con, clk_src, i2s_src, div; in rk3568_i2s3_set_rate() local
2433 clk_src = CLK_I2S3_SRC_SEL_GPLL; in rk3568_i2s3_set_rate()
2437 clk_src = CLK_I2S3_SRC_SEL_CPLL; in rk3568_i2s3_set_rate()
2441 clk_src = CLK_I2S3_SRC_SEL_GPLL; in rk3568_i2s3_set_rate()
[all …]
H A Dclk_rv1106.c862 u32 reg, clk_src, uart_src, div; in rv1106_uart_set_rate() local
866 clk_src = CLK_UART_SRC_SEL_GPLL; in rv1106_uart_set_rate()
870 clk_src = CLK_UART_SRC_SEL_CPLL; in rv1106_uart_set_rate()
874 clk_src = CLK_UART_SRC_SEL_GPLL; in rv1106_uart_set_rate()
878 clk_src = CLK_UART_SRC_SEL_GPLL; in rv1106_uart_set_rate()
912 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rv1106_uart_set_rate()
H A Dclk_rk3562.c525 u32 reg, clk_src, uart_src, div; in rk3562_uart_set_rate() local
588 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3562_uart_set_rate()
592 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3562_uart_set_rate()
596 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3562_uart_set_rate()
600 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3562_uart_set_rate()
612 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3562_uart_set_rate()
H A Dclk_px30.c429 u32 clk_src = GPLL_HZ / 2; in px30_i2s_get_clk() local
450 return clk_src * n / m; in px30_i2s_get_clk()
455 u32 clk_src; in px30_i2s_set_clk() local
459 clk_src = GPLL_HZ / 2; in px30_i2s_set_clk()
460 rational_best_approximation(hz, clk_src, in px30_i2s_set_clk()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h67 struct clk_src *src;
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h67 struct clk_src *src;