Lines Matching refs:clk_src
2283 u32 reg, clk_src, uart_src, div; in rk3568_uart_set_rate() local
2287 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2291 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3568_uart_set_rate()
2295 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2299 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2342 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3568_uart_set_rate()
2429 u32 reg, con, clk_src, i2s_src, div; in rk3568_i2s3_set_rate() local
2433 clk_src = CLK_I2S3_SRC_SEL_GPLL; in rk3568_i2s3_set_rate()
2437 clk_src = CLK_I2S3_SRC_SEL_CPLL; in rk3568_i2s3_set_rate()
2441 clk_src = CLK_I2S3_SRC_SEL_GPLL; in rk3568_i2s3_set_rate()
2445 clk_src = CLK_I2S3_SRC_SEL_GPLL; in rk3568_i2s3_set_rate()
2485 clk_src = (con & I2S3_MCLKOUT_SEL_MASK) in rk3568_i2s3_set_rate()
2487 if (clk_src == I2S3_MCLKOUT_SEL_RX) in rk3568_i2s3_set_rate()
2505 (clk_src << CLK_I2S3_SRC_SEL_SHIFT) | in rk3568_i2s3_set_rate()