Lines Matching refs:clk_src
1704 u32 reg, clk_src, p_rate; in rk3576_uart_frac_set_rate() local
1708 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3576_uart_frac_set_rate()
1711 clk_src = CLK_UART_SRC_SEL_OSC; in rk3576_uart_frac_set_rate()
1714 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3576_uart_frac_set_rate()
1751 (clk_src << CLK_UART_SRC_SEL_SHIFT)); in rk3576_uart_frac_set_rate()
1839 u32 reg, clk_src = 0, div = 0; in rk3576_uart_set_rate() local
1842 clk_src = CLK_UART_SEL_GPLL; in rk3576_uart_set_rate()
1845 clk_src = CLK_UART_SEL_CPLL; in rk3576_uart_set_rate()
1848 clk_src = CLK_UART_SEL_FRAC0; in rk3576_uart_set_rate()
1851 clk_src = CLK_UART_SEL_FRAC1; in rk3576_uart_set_rate()
1854 clk_src = CLK_UART_SEL_FRAC2; in rk3576_uart_set_rate()
1857 clk_src = CLK_UART_SEL_OSC; in rk3576_uart_set_rate()
1875 (clk_src << CLK_UART1_SRC_SEL_SHIFT) | in rk3576_uart_set_rate()
1919 (clk_src << CLK_UART_SEL_SHIFT) | in rk3576_uart_set_rate()