Lines Matching refs:clk_src
1387 u32 reg, clk_src, uart_src, div; in rk3588_uart_set_rate() local
1391 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1395 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3588_uart_set_rate()
1399 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1403 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1446 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3588_uart_set_rate()
1497 u32 clk_src, div; in rk3588_pciephy_set_rate() local
1500 clk_src = CLK_PCIE_PHY_REF_SEL_24M; in rk3588_pciephy_set_rate()
1503 clk_src = CLK_PCIE_PHY_REF_SEL_PPLL; in rk3588_pciephy_set_rate()
1511 (clk_src << CLK_PCIE_PHY0_REF_SEL_SHIFT)); in rk3588_pciephy_set_rate()
1519 (clk_src << CLK_PCIE_PHY1_REF_SEL_SHIFT)); in rk3588_pciephy_set_rate()
1528 (clk_src << CLK_PCIE_PHY2_REF_SEL_SHIFT) | in rk3588_pciephy_set_rate()