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/rk3399_rockchip-uboot/cmd/
H A Dflash.c52 int bank, first, last; in abbrev_spec() local
59 bank = simple_strtoul (str, &ep, 10); in abbrev_spec()
61 bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS || in abbrev_spec()
62 (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) in abbrev_spec()
95 ulong bank, sector_end_addr; in flash_sect_roundb() local
101 for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS && !found; ++bank) { in flash_sect_roundb()
102 info = &flash_info[bank]; in flash_sect_roundb()
194 ulong bank; in flash_fill_sect_ranges() local
199 for (bank=0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { in flash_fill_sect_ranges()
200 s_first[bank] = -1; /* first sector to erase */ in flash_fill_sect_ranges()
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Domap_gpio.c55 static void _set_gpio_direction(const struct gpio_bank *bank, int gpio, in _set_gpio_direction() argument
58 void *reg = bank->base; in _set_gpio_direction()
75 static int _get_gpio_direction(const struct gpio_bank *bank, int gpio) in _get_gpio_direction() argument
77 void *reg = bank->base; in _get_gpio_direction()
90 static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, in _set_gpio_dataout() argument
93 void *reg = bank->base; in _set_gpio_dataout()
105 static int _get_gpio_value(const struct gpio_bank *bank, int gpio) in _get_gpio_value() argument
107 void *reg = bank->base; in _get_gpio_value()
110 input = _get_gpio_direction(bank, gpio); in _get_gpio_value()
146 const struct gpio_bank *bank; in gpio_set_value() local
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H A Dintel_ich6_gpio.c57 static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset, in _ich6_gpio_set_value() argument
62 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
63 val = bank->lvl_write_cache; in _ich6_gpio_set_value()
65 val = inl(bank->lvl); in _ich6_gpio_set_value()
71 outl(val, bank->lvl); in _ich6_gpio_set_value()
72 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
73 bank->lvl_write_cache = val; in _ich6_gpio_set_value()
123 struct ich6_bank_priv *bank = dev_get_priv(dev); in ich6_gpio_probe() local
128 bank->use_sel = plat->base_addr; in ich6_gpio_probe()
129 bank->io_sel = plat->base_addr + 4; in ich6_gpio_probe()
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H A Ds5p_gpio.c38 struct s5p_gpio_bank *bank; member
44 struct s5p_gpio_bank *bank; member
60 struct s5p_gpio_bank *bank; in s5p_gpio_get_bank() local
61 bank = (struct s5p_gpio_bank *)data->reg_addr; in s5p_gpio_get_bank()
62 bank += (gpio - upto) / GPIO_PER_BANK; in s5p_gpio_get_bank()
63 debug("gpio=%d, bank=%p\n", gpio, bank); in s5p_gpio_get_bank()
64 return bank; in s5p_gpio_get_bank()
74 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) in s5p_gpio_cfg_pin() argument
78 value = readl(&bank->con); in s5p_gpio_cfg_pin()
81 writel(value, &bank->con); in s5p_gpio_cfg_pin()
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H A Dkona_gpio.c21 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) argument
22 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) argument
23 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) argument
24 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) argument
25 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) argument
26 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) argument
27 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) argument
28 #define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) argument
29 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) argument
H A Dhi6220_gpio.c16 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_direction_input() local
19 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
21 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
29 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_set_value() local
31 writeb(!!value << gpio, bank->base + (BIT(gpio + 2))); in hi6220_gpio_set_value()
38 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_direction_output() local
41 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_output()
43 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_output()
52 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_get_value() local
54 return !!readb(bank->base + (BIT(gpio + 2))); in hi6220_gpio_get_value()
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/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3576.c14 static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3576_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3576_set_mux()
23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rk3576_set_mux()
26 reg = bank->iomux[iomux_num].offset; in rk3576_set_mux()
35 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rk3576_set_mux()
56 static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3576_calc_drv_reg_and_bit() argument
60 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3576_calc_drv_reg_and_bit()
63 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_drv_reg_and_bit()
65 else if (bank->bank_num == 0) in rk3576_calc_drv_reg_and_bit()
67 else if (bank->bank_num == 1) in rk3576_calc_drv_reg_and_bit()
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H A Dpinctrl-rockchip-core.c21 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
26 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
27 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
40 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
43 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux()
50 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
64 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
67 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_mux_route()
74 if (data->bank_num == bank->bank_num && in rockchip_get_mux_route()
114 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
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H A Dpinctrl-rv1126b.c14 static int rv1126b_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rv1126b_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1126b_set_mux()
23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rv1126b_set_mux()
26 reg = bank->iomux[iomux_num].offset; in rv1126b_set_mux()
32 if (bank->recalced_mask & BIT(pin)) in rv1126b_set_mux()
33 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask); in rv1126b_set_mux()
50 static int rv1126b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rv1126b_calc_drv_reg_and_bit() argument
54 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1126b_calc_drv_reg_and_bit()
57 switch (bank->bank_num) { in rv1126b_calc_drv_reg_and_bit()
72 *reg = RV1126B_DRV_GPIO_OFFSET(bank->bank_num); in rv1126b_calc_drv_reg_and_bit()
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H A Dpinctrl-rk3506.c14 static int rockchip_set_rmio(struct rockchip_pin_bank *bank, int pin, int *mux) in rockchip_set_rmio() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_set_rmio()
29 if (bank->bank_num == 0) { in rockchip_set_rmio()
34 } else if (bank->bank_num == 1) { in rockchip_set_rmio()
48 bank->bank_num, function); in rockchip_set_rmio()
62 static int rk3506_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3506_set_mux() argument
64 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3506_set_mux()
71 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rk3506_set_mux()
73 ret = rockchip_set_rmio(bank, pin, &mux); in rk3506_set_mux()
77 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3506_set_mux()
[all …]
H A Dpinctrl-rv1108.c78 static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rv1108_set_mux() argument
80 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_set_mux()
87 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rv1108_set_mux()
91 mux_type = bank->iomux[iomux_num].type; in rv1108_set_mux()
92 reg = bank->iomux[iomux_num].offset; in rv1108_set_mux()
95 if (bank->recalced_mask & BIT(pin)) in rv1108_set_mux()
96 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask); in rv1108_set_mux()
108 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_pull_reg_and_bit() argument
112 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_pull_reg_and_bit()
115 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
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H A Dpinctrl-rk1808.c53 static int rk1808_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk1808_set_mux() argument
55 struct rockchip_pinctrl_priv *priv = bank->priv; in rk1808_set_mux()
62 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rk1808_set_mux()
64 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk1808_set_mux()
66 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rk1808_set_mux()
72 mux_type = bank->iomux[iomux_num].type; in rk1808_set_mux()
73 reg = bank->iomux[iomux_num].offset; in rk1808_set_mux()
84 if (bank->recalced_mask & BIT(pin)) in rk1808_set_mux()
85 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask); in rk1808_set_mux()
100 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk1808_calc_pull_reg_and_bit() argument
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H A Dpinctrl-rk3562.c14 static int rk3562_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3562_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3562_set_mux()
23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rk3562_set_mux()
26 reg = bank->iomux[iomux_num].offset; in rk3562_set_mux()
36 if (bank->bank_num == 1) { in rk3562_set_mux()
61 static void rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3562_calc_drv_reg_and_bit() argument
65 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3562_calc_drv_reg_and_bit()
68 switch (bank->bank_num) { in rk3562_calc_drv_reg_and_bit()
91 dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3562_calc_drv_reg_and_bit()
100 static int rk3562_set_drive(struct rockchip_pin_bank *bank, in rk3562_set_drive() argument
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H A Dpinctrl-rk3288.c31 static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3288_set_mux() argument
33 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_set_mux()
40 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3288_set_mux()
44 mux_type = bank->iomux[iomux_num].type; in rk3288_set_mux()
45 reg = bank->iomux[iomux_num].offset; in rk3288_set_mux()
49 if (bank->bank_num == 0) { in rk3288_set_mux()
66 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_pull_reg_and_bit() argument
70 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_calc_pull_reg_and_bit()
73 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
82 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
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H A Dpinctrl-rk3368.c14 static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3368_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_set_mux()
23 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rk3368_set_mux()
27 mux_type = bank->iomux[iomux_num].type; in rk3368_set_mux()
28 reg = bank->iomux[iomux_num].offset; in rk3368_set_mux()
41 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_pull_reg_and_bit() argument
45 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_calc_pull_reg_and_bit()
48 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
57 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
66 static int rk3368_set_pull(struct rockchip_pin_bank *bank, in rk3368_set_pull() argument
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H A Dpinctrl-rv1103b.c14 static int rv1103b_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rv1103b_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1103b_set_mux()
23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rv1103b_set_mux()
25 if (bank->bank_num == 2 && pin >= 12) in rv1103b_set_mux()
29 reg = bank->iomux[iomux_num].offset; in rv1103b_set_mux()
35 if (bank->recalced_mask & BIT(pin)) in rv1103b_set_mux()
36 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask); in rv1103b_set_mux()
56 static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rv1103b_calc_drv_reg_and_bit() argument
60 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1103b_calc_drv_reg_and_bit()
64 switch (bank->bank_num) { in rv1103b_calc_drv_reg_and_bit()
[all …]
H A Dpinctrl-rk3528.c14 static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rk3528_set_mux() argument
16 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3528_set_mux()
23 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rk3528_set_mux()
26 reg = bank->iomux[iomux_num].offset; in rk3528_set_mux()
50 static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3528_calc_drv_reg_and_bit() argument
54 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3528_calc_drv_reg_and_bit()
57 switch (bank->bank_num) { in rk3528_calc_drv_reg_and_bit()
80 dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3528_calc_drv_reg_and_bit()
89 static int rk3528_set_drive(struct rockchip_pin_bank *bank, in rk3528_set_drive() argument
98 rk3528_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit); in rk3528_set_drive()
[all …]
/rk3399_rockchip-uboot/drivers/irq/
H A Dirq-gpio.c86 struct gpio_bank *bank = gpio_id_to_bank(irq - IRQ_GPIO0); in generic_gpio_handle_irq() local
90 isr = readl(bank->regbase + GPIO_INT_STATUS); in generic_gpio_handle_irq()
91 ilr = readl(bank->regbase + GPIO_INTTYPE_LEVEL); in generic_gpio_handle_irq()
93 gpio_irq = bank->irq_base; in generic_gpio_handle_irq()
99 gpio_irq_mask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
100 gpio_irq_ack(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
108 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
116 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
177 struct gpio_bank *bank = gpio_to_bank(gpio); in gpio_irq_set_type() local
180 if (!bank) in gpio_irq_set_type()
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H A Dirq-gpio-v2.c91 struct gpio_bank *bank = gpio_id_to_bank(irq - IRQ_GPIO0); in generic_gpio_handle_irq() local
95 isr = readl(bank->regbase + GPIO_INT_STATUS); in generic_gpio_handle_irq()
96 ilr_l = readl(bank->regbase + GPIO_INTTYPE_LEVEL_L); in generic_gpio_handle_irq()
97 ilr_h = readl(bank->regbase + GPIO_INTTYPE_LEVEL_H); in generic_gpio_handle_irq()
98 gpio_irq = bank->irq_base; in generic_gpio_handle_irq()
104 gpio_irq_mask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
105 gpio_irq_ack(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
114 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
120 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
128 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); in generic_gpio_handle_irq()
[all …]
H A Dirq-gpio-switch.c63 int idx, bank = 0, pin = 0; in __hard_gpio_to_irq() local
69 bank = (gpio & GPIO_BANK_MASK) >> GPIO_BANK_OFFSET; in __hard_gpio_to_irq()
73 if (gpio_banks[idx].id == bank) { in __hard_gpio_to_irq()
138 int bank, ret; in lookup_gpio_bank() local
140 for (bank = 0; bank < GPIO_BANK_NUM; bank++) { in lookup_gpio_bank()
141 if (strstr(name, gpio_banks[bank].name)) in lookup_gpio_bank()
142 return bank; in lookup_gpio_bank()
146 for (bank = 0; !ret && bank < GPIO_BANK_NUM; bank++) { in lookup_gpio_bank()
151 if (strstr(aliases_gpios[bank], name)) in lookup_gpio_bank()
152 return bank; in lookup_gpio_bank()
[all …]
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dbootm-fdt.c54 int bank; in arch_fixup_fdt() local
61 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { in arch_fixup_fdt()
62 start[bank] = bd->bi_dram[bank].start; in arch_fixup_fdt()
63 size[bank] = bd->bi_dram[bank].size; in arch_fixup_fdt()
64 if (size[bank] == 0) in arch_fixup_fdt()
68 start[bank], start[bank] + size[bank], size[bank]); in arch_fixup_fdt()
71 ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); in arch_fixup_fdt()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c63 int bank; member
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
111 int bank = lanes[lane].bank; in serdes_lane_enabled() local
115 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
124 if (bank > 0) in serdes_lane_enabled()
125 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
282 static void enable_bank(ccsr_gur_t *gur, int bank) in enable_bank() argument
285 u32 temp_lpd_b = srds_lpd_b[bank]; in enable_bank()
299 if (bank == FSL_SRDS_BANK_2) { in enable_bank()
302 } else if (bank == FSL_SRDS_BANK_3) { in enable_bank()
[all …]
/rk3399_rockchip-uboot/drivers/misc/
H A Dfsl_iim.c94 } bank[8]; member
101 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert, in prepare_access() argument
106 if (bank >= ARRAY_SIZE((*regs)->bank) || in prepare_access()
107 word >= ARRAY_SIZE((*regs)->bank[0].word) || in prepare_access()
129 static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val, in prepare_read() argument
134 ret = prepare_access(regs, bank, word, val != NULL, caller); in prepare_read()
143 int fuse_read(u32 bank, u32 word, u32 *val) in fuse_read() argument
149 ret = prepare_read(&regs, bank, word, val, __func__); in fuse_read()
153 *val = iim_read32(&regs->bank[bank].word[word]); in fuse_read()
164 static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit, in direct_access() argument
[all …]
H A Dmxc_ocotp.c131 u32 fuse_word_physical(u32 bank, u32 word_index) in fuse_word_physical() argument
134 if (bank == 8) in fuse_word_physical()
146 u32 fuse_word_physical(u32 bank, u32 word_index) in fuse_word_physical() argument
164 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, in prepare_access() argument
169 if (bank >= FUSE_BANKS || in prepare_access()
170 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || in prepare_access()
177 if ((bank == 7 || bank == 8) && in prepare_access()
178 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { in prepare_access()
211 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, in prepare_read() argument
214 return prepare_access(regs, bank, word, val != NULL, caller); in prepare_read()
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/
H A Dpinctrl-sti.c48 unsigned char bank; member
62 int bank = pin_desc->bank; in sti_alternate_select() local
67 switch (bank) { in sti_alternate_select()
69 sysconfreg += bank; in sti_alternate_select()
72 sysconfreg += bank - 10; in sti_alternate_select()
75 sysconfreg += bank - 30; in sti_alternate_select()
78 sysconfreg += bank - 40; in sti_alternate_select()
97 int bank = pin_desc->bank; in sti_pin_configure() local
151 switch (bank) { in sti_pin_configure()
153 sysconfreg += bank / 4; in sti_pin_configure()
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