1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11 #include <fdtdec.h>
12 #include <dm/uclass-internal.h>
13 #include <asm/gpio.h>
14
15 #include "pinctrl-rockchip.h"
16
17 #define MAX_ROCKCHIP_PINS_ENTRIES 30
18 #define MAX_ROCKCHIP_GPIO_PER_BANK 32
19 #define RK_FUNC_GPIO 0
20
rockchip_verify_config(struct udevice * dev,u32 bank,u32 pin)21 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
22 {
23 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
24 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
25
26 if (bank >= ctrl->nr_banks) {
27 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
28 return -EINVAL;
29 }
30
31 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
32 debug("pin conf pin %d >= %d\n", pin,
33 MAX_ROCKCHIP_GPIO_PER_BANK);
34 return -EINVAL;
35 }
36
37 return 0;
38 }
39
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)40 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
41 int *reg, u8 *bit, int *mask)
42 {
43 struct rockchip_pinctrl_priv *priv = bank->priv;
44 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
45 struct rockchip_mux_recalced_data *data;
46 int i;
47
48 for (i = 0; i < ctrl->niomux_recalced; i++) {
49 data = &ctrl->iomux_recalced[i];
50 if (data->num == bank->bank_num &&
51 data->pin == pin)
52 break;
53 }
54
55 if (i >= ctrl->niomux_recalced)
56 return;
57
58 *reg = data->reg;
59 *mask = data->mask;
60 *bit = data->bit;
61 }
62
63 static enum rockchip_pin_route_type
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * reg,u32 * value)64 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
65 int mux, u32 *reg, u32 *value)
66 {
67 struct rockchip_pinctrl_priv *priv = bank->priv;
68 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
69 struct rockchip_mux_route_data *data;
70 int i;
71
72 for (i = 0; i < ctrl->niomux_routes; i++) {
73 data = &ctrl->iomux_routes[i];
74 if (data->bank_num == bank->bank_num &&
75 data->pin == pin && data->func == mux)
76 break;
77 }
78
79 if (i >= ctrl->niomux_routes)
80 return ROUTE_TYPE_INVALID;
81
82 *reg = data->route_offset;
83 *value = data->route_val;
84
85 return data->route_type;
86 }
87
rockchip_get_mux_data(int mux_type,int pin,u8 * bit,int * mask)88 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
89 {
90 int offset = 0;
91
92 if (mux_type & IOMUX_WIDTH_4BIT) {
93 if ((pin % 8) >= 4)
94 offset = 0x4;
95 *bit = (pin % 4) * 4;
96 *mask = 0xf;
97 } else if (mux_type & IOMUX_WIDTH_3BIT) {
98 /*
99 * pin0 ~ pin4 are at first register, and
100 * pin5 ~ pin7 are at second register.
101 */
102 if ((pin % 8) >= 5)
103 offset = 0x4;
104 *bit = (pin % 8 % 5) * 3;
105 *mask = 0x7;
106 } else {
107 *bit = (pin % 8) * 2;
108 *mask = 0x3;
109 }
110
111 return offset;
112 }
113
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)114 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
115 {
116 struct rockchip_pinctrl_priv *priv = bank->priv;
117 int iomux_num = (pin / 8);
118 struct regmap *regmap;
119 unsigned int val;
120 int reg, ret, mask, mux_type;
121 u8 bit;
122
123 if (iomux_num > 3)
124 return -EINVAL;
125
126 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
127 debug("pin %d is unrouted\n", pin);
128 return -ENOTSUPP;
129 }
130
131 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
132 return RK_FUNC_GPIO;
133
134 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
135 ? priv->regmap_pmu : priv->regmap_base;
136
137 /* get basic quadrupel of mux registers and the correct reg inside */
138 mux_type = bank->iomux[iomux_num].type;
139 reg = bank->iomux[iomux_num].offset;
140 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
141
142 if (bank->recalced_mask & BIT(pin))
143 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
144
145 ret = regmap_read(regmap, reg, &val);
146 if (ret)
147 return ret;
148
149 return ((val >> bit) & mask);
150 }
151
rockchip_pinctrl_get_gpio_mux(struct udevice * dev,int banknum,int index)152 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
153 int index)
154 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
155 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
156
157 return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
158 }
159
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)160 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
161 int pin, int mux)
162 {
163 int iomux_num = (pin / 8);
164
165 if (iomux_num > 3)
166 return -EINVAL;
167
168 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
169 debug("pin %d is unrouted\n", pin);
170 return -ENOTSUPP;
171 }
172
173 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
174 if (mux != IOMUX_GPIO_ONLY) {
175 debug("pin %d only supports a gpio mux\n", pin);
176 return -ENOTSUPP;
177 }
178 }
179
180 return 0;
181 }
182
183 /*
184 * Set a new mux function for a pin.
185 *
186 * The register is divided into the upper and lower 16 bit. When changing
187 * a value, the previous register value is not read and changed. Instead
188 * it seems the changed bits are marked in the upper 16 bit, while the
189 * changed value gets set in the same offset in the lower 16 bit.
190 * All pin settings seem to be 2 bit wide in both the upper and lower
191 * parts.
192 * @bank: pin bank to change
193 * @pin: pin to change
194 * @mux: new mux function to set
195 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)196 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
197 {
198 struct rockchip_pinctrl_priv *priv = bank->priv;
199 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
200 int iomux_num = (pin / 8);
201 int ret;
202
203 ret = rockchip_verify_mux(bank, pin, mux);
204 if (ret < 0)
205 return ret == -ENOTSUPP ? 0 : ret;
206
207 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
208 return 0;
209
210 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
211
212 if (!ctrl->set_mux)
213 return -ENOTSUPP;
214
215 ret = ctrl->set_mux(bank, pin, mux);
216 if (ret)
217 return ret;
218
219 if (bank->route_mask & BIT(pin)) {
220 struct regmap *regmap;
221 u32 route_reg = 0, route_val = 0;
222
223 ret = rockchip_get_mux_route(bank, pin, mux,
224 &route_reg, &route_val);
225 switch (ret) {
226 case ROUTE_TYPE_DEFAULT:
227 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
228 regmap = priv->regmap_pmu;
229 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
230 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
231 else
232 regmap = priv->regmap_base;
233
234 regmap_write(regmap, route_reg, route_val);
235 break;
236 case ROUTE_TYPE_TOPGRF:
237 regmap_write(priv->regmap_base, route_reg, route_val);
238 break;
239 case ROUTE_TYPE_PMUGRF:
240 regmap_write(priv->regmap_pmu, route_reg, route_val);
241 break;
242 case ROUTE_TYPE_INVALID: /* Fall through */
243 default:
244 break;
245 }
246 }
247
248 return 0;
249 }
250
251 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
252 { 2, 4, 8, 12, -1, -1, -1, -1 },
253 { 3, 6, 9, 12, -1, -1, -1, -1 },
254 { 5, 10, 15, 20, -1, -1, -1, -1 },
255 { 4, 6, 8, 10, 12, 14, 16, 18 },
256 { 4, 7, 10, 13, 16, 19, 22, 26 }
257 };
258
rockchip_translate_drive_value(int type,int strength)259 int rockchip_translate_drive_value(int type, int strength)
260 {
261 int i, ret;
262
263 ret = -EINVAL;
264 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
265 if (rockchip_perpin_drv_list[type][i] == strength) {
266 ret = i;
267 break;
268 } else if (rockchip_perpin_drv_list[type][i] < 0) {
269 ret = rockchip_perpin_drv_list[type][i];
270 break;
271 }
272 }
273
274 return ret;
275 }
276
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)277 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
278 int pin_num, int strength)
279 {
280 struct rockchip_pinctrl_priv *priv = bank->priv;
281 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
282
283 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
284 pin_num, strength);
285
286 if (!ctrl->set_drive)
287 return -ENOTSUPP;
288
289 return ctrl->set_drive(bank, pin_num, strength);
290 }
291
292 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
293 {
294 PIN_CONFIG_BIAS_DISABLE,
295 PIN_CONFIG_BIAS_PULL_UP,
296 PIN_CONFIG_BIAS_PULL_DOWN,
297 PIN_CONFIG_BIAS_BUS_HOLD
298 },
299 {
300 PIN_CONFIG_BIAS_DISABLE,
301 PIN_CONFIG_BIAS_PULL_DOWN,
302 PIN_CONFIG_BIAS_DISABLE,
303 PIN_CONFIG_BIAS_PULL_UP
304 },
305 };
306
rockchip_translate_pull_value(int type,int pull)307 int rockchip_translate_pull_value(int type, int pull)
308 {
309 int i, ret;
310
311 ret = -EINVAL;
312 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
313 i++) {
314 if (rockchip_pull_list[type][i] == pull) {
315 ret = i;
316 break;
317 }
318 }
319
320 return ret;
321 }
322
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)323 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
324 int pin_num, int pull)
325 {
326 struct rockchip_pinctrl_priv *priv = bank->priv;
327 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
328
329 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
330 pin_num, pull);
331
332 if (!ctrl->set_pull)
333 return -ENOTSUPP;
334
335 return ctrl->set_pull(bank, pin_num, pull);
336 }
337
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)338 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
339 int pin_num, int enable)
340 {
341 struct rockchip_pinctrl_priv *priv = bank->priv;
342 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
343
344 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
345 pin_num, enable);
346
347 if (!ctrl->set_schmitt)
348 return -ENOTSUPP;
349
350 return ctrl->set_schmitt(bank, pin_num, enable);
351 }
352
353 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct rockchip_pin_bank * bank,u32 pin,u32 param,u32 arg)354 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
355 u32 pin, u32 param, u32 arg)
356 {
357 int rc;
358 #if CONFIG_IS_ENABLED(DM_GPIO) && \
359 (CONFIG_IS_ENABLED(SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD))
360 struct gpio_desc desc;
361 char gpio_name[16];
362 #endif
363
364 switch (param) {
365 case PIN_CONFIG_BIAS_DISABLE:
366 case PIN_CONFIG_BIAS_PULL_UP:
367 case PIN_CONFIG_BIAS_PULL_DOWN:
368 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
369 case PIN_CONFIG_BIAS_BUS_HOLD:
370 rc = rockchip_set_pull(bank, pin, param);
371 if (rc)
372 return rc;
373 break;
374
375 case PIN_CONFIG_DRIVE_STRENGTH:
376 rc = rockchip_set_drive_perpin(bank, pin, arg);
377 if (rc < 0)
378 return rc;
379 break;
380
381 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
382 rc = rockchip_set_schmitt(bank, pin, arg);
383 if (rc < 0)
384 return rc;
385 break;
386
387 case PIN_CONFIG_OUTPUT:
388 #if CONFIG_IS_ENABLED(DM_GPIO) && \
389 (CONFIG_IS_ENABLED(SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD))
390 desc.flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
391 if (!arg) desc.flags |= GPIOD_ACTIVE_LOW;
392 snprintf(gpio_name, 16, "%s%d", bank->name, pin);
393 rc = dm_gpio_lookup_name(gpio_name, &desc);
394 if (rc < 0) {
395 debug("%s: GPIO %s-%d lookup failed (ret=%d)\n", __func__,
396 bank->name, pin, rc);
397 return rc;
398 }
399
400 rc = dm_gpio_request(&desc, gpio_name);
401 if (rc < 0) {
402 debug("%s: GPIO %s-%d request failed (ret=%d)\n", __func__,
403 bank->name, pin, rc);
404 return rc;
405 }
406 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
407 dm_gpio_set_value(&desc, arg ? 1 : 0);
408 debug("%s: GPIO %s-%d set to %d\n", __func__, bank->name, pin, arg);
409 #else
410 return -ENOSYS;
411 #endif
412 break;
413 default:
414 break;
415 }
416
417 return 0;
418 }
419
420 static const struct pinconf_param rockchip_conf_params[] = {
421 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
422 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
423 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
424 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
425 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
426 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
427 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
428 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
429 { "output-high", PIN_CONFIG_OUTPUT, 1, },
430 { "output-low", PIN_CONFIG_OUTPUT, 0, },
431 };
432
rockchip_pinconf_prop_name_to_param(const char * property,u32 * default_value)433 static int rockchip_pinconf_prop_name_to_param(const char *property,
434 u32 *default_value)
435 {
436 const struct pinconf_param *p, *end;
437
438 p = rockchip_conf_params;
439 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
440
441 /* See if this pctldev supports this parameter */
442 for (; p < end; p++) {
443 if (!strcmp(property, p->property)) {
444 *default_value = p->default_value;
445 return p->param;
446 }
447 }
448
449 *default_value = 0;
450 return -EPERM;
451 }
452
rockchip_pinctrl_set_state(struct udevice * dev,struct udevice * config)453 static int rockchip_pinctrl_set_state(struct udevice *dev,
454 struct udevice *config)
455 {
456 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
457 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
458 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
459 u32 bank, pin, mux, conf, arg, default_val;
460 int ret, count, i;
461 const char *prop_name;
462 const void *value;
463 int prop_len, param;
464 const u32 *data;
465 ofnode node;
466 #if CONFIG_IS_ENABLED(OF_LIVE)
467 const struct device_node *np;
468 struct property *pp;
469 #else
470 int property_offset, pcfg_node;
471 const void *blob = gd->fdt_blob;
472 #endif
473 data = dev_read_prop(config, "rockchip,pins", &count);
474 if (count < 0) {
475 debug("%s: bad array size %d\n", __func__, count);
476 return -EINVAL;
477 }
478
479 count /= sizeof(u32);
480 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
481 debug("%s: unsupported pins array count %d\n",
482 __func__, count);
483 return -EINVAL;
484 }
485
486 for (i = 0; i < count; i++)
487 cells[i] = fdt32_to_cpu(data[i]);
488
489 for (i = 0; i < (count >> 2); i++) {
490 bank = cells[4 * i + 0];
491 pin = cells[4 * i + 1];
492 mux = cells[4 * i + 2];
493 conf = cells[4 * i + 3];
494
495 ret = rockchip_verify_config(dev, bank, pin);
496 if (ret)
497 return ret;
498
499 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
500 if (ret)
501 return ret;
502
503 node = ofnode_get_by_phandle(conf);
504 if (!ofnode_valid(node))
505 return -ENODEV;
506 #if CONFIG_IS_ENABLED(OF_LIVE)
507 np = ofnode_to_np(node);
508 for (pp = np->properties; pp; pp = pp->next) {
509 prop_name = pp->name;
510 prop_len = pp->length;
511 value = pp->value;
512 #else
513 pcfg_node = ofnode_to_offset(node);
514 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
515 value = fdt_getprop_by_offset(blob, property_offset,
516 &prop_name, &prop_len);
517 if (!value)
518 return -ENOENT;
519 #endif
520 param = rockchip_pinconf_prop_name_to_param(prop_name,
521 &default_val);
522 if (param < 0)
523 break;
524
525 if (prop_len >= sizeof(fdt32_t))
526 arg = fdt32_to_cpu(*(fdt32_t *)value);
527 else
528 arg = default_val;
529
530 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
531 param, arg);
532 if (ret) {
533 debug("%s: rockchip_pinconf_set fail: %d\n",
534 __func__, ret);
535 return ret;
536 }
537 }
538 }
539
540 return 0;
541 }
542
543 static int rockchip_pinctrl_get_pins_count(struct udevice *dev)
544 {
545 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
546 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
547
548 return ctrl->nr_pins;
549 }
550
551 const struct pinctrl_ops rockchip_pinctrl_ops = {
552 .get_pins_count = rockchip_pinctrl_get_pins_count,
553 .set_state = rockchip_pinctrl_set_state,
554 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
555 };
556
557 /* retrieve the soc specific data */
558 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
559 {
560 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
561 struct rockchip_pin_ctrl *ctrl =
562 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
563 struct rockchip_pin_bank *bank;
564 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
565 u32 nr_pins;
566
567 grf_offs = ctrl->grf_mux_offset;
568 pmu_offs = ctrl->pmu_mux_offset;
569 drv_pmu_offs = ctrl->pmu_drv_offset;
570 drv_grf_offs = ctrl->grf_drv_offset;
571 bank = ctrl->pin_banks;
572
573 nr_pins = 0;
574 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
575 int bank_pins = 0;
576
577 bank->priv = priv;
578 bank->pin_base = nr_pins;
579 nr_pins += bank->nr_pins;
580
581 /* calculate iomux and drv offsets */
582 for (j = 0; j < 4; j++) {
583 struct rockchip_iomux *iom = &bank->iomux[j];
584 struct rockchip_drv *drv = &bank->drv[j];
585 int inc;
586
587 if (bank_pins >= nr_pins)
588 break;
589
590 /* preset iomux offset value, set new start value */
591 if (iom->offset >= 0) {
592 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
593 pmu_offs = iom->offset;
594 else
595 grf_offs = iom->offset;
596 } else { /* set current iomux offset */
597 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
598 (iom->type & IOMUX_L_SOURCE_PMU)) ?
599 pmu_offs : grf_offs;
600 }
601
602 /* preset drv offset value, set new start value */
603 if (drv->offset >= 0) {
604 if (iom->type & IOMUX_SOURCE_PMU)
605 drv_pmu_offs = drv->offset;
606 else
607 drv_grf_offs = drv->offset;
608 } else { /* set current drv offset */
609 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
610 drv_pmu_offs : drv_grf_offs;
611 }
612
613 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
614 i, j, iom->offset, drv->offset);
615
616 /*
617 * Increase offset according to iomux width.
618 * 4bit iomux'es are spread over two registers.
619 */
620 inc = (iom->type & (IOMUX_WIDTH_4BIT |
621 IOMUX_WIDTH_3BIT |
622 IOMUX_8WIDTH_2BIT)) ? 8 : 4;
623 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
624 pmu_offs += inc;
625 else
626 grf_offs += inc;
627
628 /*
629 * Increase offset according to drv width.
630 * 3bit drive-strenth'es are spread over two registers.
631 */
632 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
633 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
634 inc = 8;
635 else
636 inc = 4;
637
638 if (iom->type & IOMUX_SOURCE_PMU)
639 drv_pmu_offs += inc;
640 else
641 drv_grf_offs += inc;
642
643 bank_pins += 8;
644 }
645
646 /* calculate the per-bank recalced_mask */
647 for (j = 0; j < ctrl->niomux_recalced; j++) {
648 int pin = 0;
649
650 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
651 pin = ctrl->iomux_recalced[j].pin;
652 bank->recalced_mask |= BIT(pin);
653 }
654 }
655
656 /* calculate the per-bank route_mask */
657 for (j = 0; j < ctrl->niomux_routes; j++) {
658 int pin = 0;
659
660 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
661 pin = ctrl->iomux_routes[j].pin;
662 bank->route_mask |= BIT(pin);
663 }
664 }
665 }
666
667 WARN_ON(nr_pins != ctrl->nr_pins);
668
669 return ctrl;
670 }
671
672 int rockchip_pinctrl_probe(struct udevice *dev)
673 {
674 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
675 struct rockchip_pin_ctrl *ctrl;
676 struct udevice *syscon;
677 struct regmap *regmap;
678 int ret = 0;
679
680 /* get rockchip grf syscon phandle */
681 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
682 &syscon);
683 if (ret) {
684 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
685 return ret;
686 }
687
688 /* get grf-reg base address */
689 regmap = syscon_get_regmap(syscon);
690 if (!regmap) {
691 debug("unable to find rockchip grf regmap\n");
692 return -ENODEV;
693 }
694 priv->regmap_base = regmap;
695
696 /* option: get pmu-reg base address */
697 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
698 &syscon);
699 if (!ret) {
700 /* get pmugrf-reg base address */
701 regmap = syscon_get_regmap(syscon);
702 if (!regmap) {
703 debug("unable to find rockchip pmu regmap\n");
704 return -ENODEV;
705 }
706 priv->regmap_pmu = regmap;
707 }
708
709 /* option: get ioc1-reg base address */
710 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,ioc1",
711 &syscon);
712 if (!ret) {
713 /* get ioc1-reg base address */
714 regmap = syscon_get_regmap(syscon);
715 if (!regmap) {
716 debug("unable to find rockchip ioc1 regmap\n");
717 return -ENODEV;
718 }
719 priv->regmap_ioc1 = regmap;
720 }
721
722 /* option: get rmio-reg base address */
723 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,rmio",
724 &syscon);
725 if (!ret) {
726 /* get pmugrf-reg base address */
727 regmap = syscon_get_regmap(syscon);
728 if (!regmap) {
729 debug("unable to find rockchip rmio regmap\n");
730 return -ENODEV;
731 }
732 priv->regmap_rmio = regmap;
733 }
734
735 ctrl = rockchip_pinctrl_get_soc_data(dev);
736 if (!ctrl) {
737 debug("driver data not available\n");
738 return -EINVAL;
739 }
740
741 priv->ctrl = ctrl;
742 return 0;
743 }
744