dm: core: Replace of_offset with accessor (part 2)

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
devi

dm: core: Replace of_offset with accessor (part 2)

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-x86

x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This

x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).

Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.

This also resolves the 'gpio clear | set' command warning like:
"Warning: value of pin is still 0"

Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-dm

dm: core: Replace of_offset with accessor

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree,

dm: core: Replace of_offset with accessor

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: Probe pinctrl driver in cpu_init_r()

At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

- Pin's PADs only gets configured when GPIO driver is pro

x86: Probe pinctrl driver in cpu_init_r()

At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

- Pin's PADs only gets configured when GPIO driver is probed, which
is not done by default. This leaves the board in a partially
functional state as we must initialize PADs correctly to get
perepherals fully working.
- The probe routine of pinctrl driver is called multiple times, as
normally there are multiple GPIO controllers. It should really
be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>

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x86: ich6_gpio: Output return value of syscon_get_by_driver_data()

The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng <bm

x86: ich6_gpio: Output return value of syscon_get_by_driver_data()

The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: Drop all the old pin configuration code

We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin

x86: Drop all the old pin configuration code

We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: gpio: Allow the pinctrl driver to set up the pin config

Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.

Signed-off-by: Simon Glass <sjg@ch

x86: gpio: Allow the pinctrl driver to set up the pin config

Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: gpio: Correct GPIO setup ordering

The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO

x86: gpio: Correct GPIO setup ordering

The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ich6_gpio: Convert to use proper DM API

At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While

x86: ich6_gpio: Convert to use proper DM API

At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-x86

x86: gpio: Tidy up gpio_ich6_get_base() and callers

This function can return an error. Correct the detection of this error so
that it works even with large 32-bit addresses.

The return value is set

x86: gpio: Tidy up gpio_ich6_get_base() and callers

This function can return an error. Correct the detection of this error so
that it works even with large 32-bit addresses.

The return value is set up for returning an I/O address but the function is
also used to return a memory-mapped address. Adjust the return code to make
this work.

Also add a bit more debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>

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x86: gpio: Correct calls to _ich6_gpio_set_direction()

These calls seem to be incorrect. The function expects an I/O address but
the existing callers pass the value at an I/O address. Fix it.

Signe

x86: gpio: Correct calls to _ich6_gpio_set_direction()

These calls seem to be incorrect. The function expects an I/O address but
the existing callers pass the value at an I/O address. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-x86

x86: Add some missing global_data declarations in files that use gd

Some files use global_data but don't declare it. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <b

x86: Add some missing global_data declarations in files that use gd

Some files use global_data but don't declare it. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

x86: gpio: add pinctrl support from the device tree

Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668

x86: gpio: add pinctrl support from the device tree

Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

dm: core: Add dev_get_uclass_priv() to access uclass private data

Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses

dm: core: Add dev_get_uclass_priv() to access uclass private data

Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.

Signed-off-by: Simon Glass <sjg@chromium.org>

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x86: Add a x86_ prefix to the x86-specific PCI functions

These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these na

x86: Add a x86_ prefix to the x86-specific PCI functions

These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-x86

x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address regis

x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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