| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clk.h | 16 #define VPLL 4 macro
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/ |
| H A D | clock.c | 145 } else if (pllreg == VPLL) { in exynos_get_pll_clk()
203 case VPLL: in exynos4_get_pll_clk()
233 case VPLL: in exynos4x12_get_pll_clk()
264 case VPLL: in exynos5_get_pll_clk()
322 case VPLL: in exynos542x_get_pll_clk()
444 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
657 sclk = get_pll_clk(VPLL); in exynos4_get_pwm_clk()
718 sclk = get_pll_clk(VPLL); in exynos4_get_uart_clk()
764 sclk = get_pll_clk(VPLL); in exynos4x12_get_uart_clk()
800 sclk = get_pll_clk(VPLL); in exynos4_get_mmc_clk()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 15 #define VPLL 4 macro
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3576.c | 71 [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
1213 pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], in rk3576_dclk_vop_set_clk()
1214 priv->cru, VPLL); in rk3576_dclk_vop_set_clk()
1229 rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], in rk3576_dclk_vop_set_clk()
1230 priv->cru, VPLL, div * rate); in rk3576_dclk_vop_set_clk()
1231 priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], in rk3576_dclk_vop_set_clk()
1232 priv->cru, VPLL); in rk3576_dclk_vop_set_clk()
1445 pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], in rk3576_dclk_ebc_set_clk()
1446 priv->cru, VPLL); in rk3576_dclk_ebc_set_clk()
1461 rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], in rk3576_dclk_ebc_set_clk()
[all …]
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| H A D | clk_rk3562.c | 51 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
1147 rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_vop_get_rate()
1148 priv->cru, VPLL); in rk3562_vop_get_rate()
1209 rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_vop_set_rate()
1210 VPLL, div * rate); in rk3562_vop_set_rate()
1376 rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_get_rate()
1377 VPLL); in rk3562_clk_get_rate()
1504 ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_set_rate()
1505 VPLL, rate); in rk3562_clk_set_rate()
1506 priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_clk_set_rate()
[all …]
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| H A D | clk_rk3568.c | 78 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
1806 parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], in rk3568_dclk_vop_get_clk()
1807 priv->cru, VPLL); in rk3568_dclk_vop_get_clk()
1859 rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], in rk3568_dclk_vop_set_clk()
1860 priv->cru, VPLL, div * rate); in rk3568_dclk_vop_set_clk()
2546 rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru, in rk3568_clk_get_rate()
2547 VPLL); in rk3568_clk_get_rate()
2733 ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru, in rk3568_clk_set_rate()
2734 VPLL, rate); in rk3568_clk_set_rate()
2735 priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], in rk3568_clk_set_rate()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 94 case VPLL: in s5pc110_get_pll_clk()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/video/ |
| H A D | exynos-fb.txt | 55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3562.h | 26 VPLL, enumerator
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| H A D | cru_rk3568.h | 26 VPLL, enumerator
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| H A D | cru_rk3576.h | 28 VPLL, enumerator
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| /rk3399_rockchip-uboot/board/samsung/goni/ |
| H A D | lowlevel_init.S | 334 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
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