clk/rockchip/clk_rk3562.c

51 	[VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
1147 				rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],  in rk3562_vop_get_rate()
1148 						      priv->cru, VPLL);  in rk3562_vop_get_rate()
1209 		rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,  in rk3562_vop_set_rate()
1210 				      VPLL, div * rate);  in rk3562_vop_set_rate()
1376 		rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru,  in rk3562_clk_get_rate()
1377 					     VPLL);  in rk3562_clk_get_rate()
1504 		ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,  in rk3562_clk_set_rate()
1505 					    VPLL, rate);  in rk3562_clk_set_rate()
1506 		priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],  in rk3562_clk_set_rate()
1507 						      priv->cru, VPLL);  in rk3562_clk_set_rate()