71 	[VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
1213 		pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_vop_set_clk()
1214 						 priv->cru, VPLL);  in rk3576_dclk_vop_set_clk()
1229 			rockchip_pll_set_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_vop_set_clk()
1230 					      priv->cru, VPLL, div * rate);  in rk3576_dclk_vop_set_clk()
1231 			priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_vop_set_clk()
1232 							      priv->cru, VPLL);  in rk3576_dclk_vop_set_clk()
1445 			pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_ebc_set_clk()
1446 							 priv->cru, VPLL);  in rk3576_dclk_ebc_set_clk()
1461 				rockchip_pll_set_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_ebc_set_clk()
1463 						      VPLL, div * rate);  in rk3576_dclk_ebc_set_clk()
1464 				priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_ebc_set_clk()
1466 								      VPLL);  in rk3576_dclk_ebc_set_clk()
2087 		rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], priv->cru,  in rk3576_clk_get_rate()
2088 					     VPLL);  in rk3576_clk_get_rate()
2249 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], priv->cru,  in rk3576_clk_set_rate()
2250 					    VPLL, rate);  in rk3576_clk_set_rate()
2251 		priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_clk_set_rate()
2252 						       priv->cru, VPLL);  in rk3576_clk_set_rate()