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Searched refs:PPLL_HZ (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h85 #define PPLL_HZ (676*MHz) macro
H A Dcru_rk3528.h18 #define PPLL_HZ (1000 * MHz) macro
H A Dcru_rk3588.h19 #define PPLL_HZ (1100 * MHz) macro
H A Dcru_rk3568.h17 #define PPLL_HZ (200 * MHz) macro
H A Dcru_rk3576.h18 #define PPLL_HZ (1100 * MHz) macro
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3399.c54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
1621 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_i2c_get_pmuclk()
1629 src_clk_div = PPLL_HZ / hz; in rk3399_i2c_set_pmuclk()
1650 return DIV_TO_RATE(PPLL_HZ, src_clk_div); in rk3399_i2c_set_pmuclk()
1661 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_pwm_get_clk()
1721 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; in pmuclk_init()
H A Dclk_rk3528.c1956 if (priv->ppll_hz != PPLL_HZ) { in rk3528_clk_init()
1958 PPLL, PPLL_HZ); in rk3528_clk_init()
1960 priv->ppll_hz = PPLL_HZ; in rk3528_clk_init()
H A Dclk_rk3568.c493 if (priv->ppll_hz != PPLL_HZ) { in rk3568_pmuclk_probe()
496 PPLL, PPLL_HZ); in rk3568_pmuclk_probe()
498 priv->ppll_hz = PPLL_HZ; in rk3568_pmuclk_probe()
H A Dclk_rk3588.c2084 if (priv->ppll_hz != PPLL_HZ) { in rk3588_clk_init()
2086 PPLL, PPLL_HZ); in rk3588_clk_init()