| /rk3399_rockchip-uboot/include/dt-bindings/clock/ |
| H A D | rk3188-cru-common.h | 14 #define PLL_CPLL 3 macro
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| H A D | rk3128-cru.h | 13 #define PLL_CPLL 3 macro
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| H A D | rk3228-cru.h | 13 #define PLL_CPLL 3 macro
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| H A D | px30-cru.h | 22 #define PLL_CPLL 3 macro
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| H A D | rk3328-cru.h | 13 #define PLL_CPLL 3 macro
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| H A D | rk3288-cru.h | 11 #define PLL_CPLL 3 macro
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| H A D | rk3368-cru.h | 22 #define PLL_CPLL 4 macro
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| H A D | rk1808-cru.h | 9 #define PLL_CPLL 3 macro
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| H A D | rv1106-cru.h | 13 #define PLL_CPLL 3 macro
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| H A D | rv1126-cru.h | 67 #define PLL_CPLL 3 macro
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| H A D | rk3562-cru.h | 17 #define PLL_CPLL 5 macro
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| H A D | rk3528-cru.h | 14 #define PLL_CPLL 2 macro
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| H A D | rk3399-cru.h | 16 #define PLL_CPLL 4 macro
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| H A D | rockchip,rv1126b-cru.h | 12 #define PLL_CPLL 2 macro
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk322x.c | 69 RK322x_CLK_DUMP(PLL_CPLL, "cpll", true),
86 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(6),
584 case PLL_CPLL: in rk322x_clk_get_rate()
648 case PLL_CPLL: in rk322x_clk_set_rate()
772 else if (parent->id == PLL_CPLL) in rk322x_lcdc_set_parent()
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| H A D | clk_rk3128.c | 68 RK3128_CLK_DUMP(PLL_CPLL, "cpll", true),
85 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(8),
537 case PLL_CPLL: in rk3128_clk_get_rate()
601 case PLL_CPLL: in rk3128_clk_set_rate()
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| H A D | clk_rk3328.c | 92 RK3328_CLK_DUMP(PLL_CPLL, "cpll", true),
110 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3328_PLL_CON(16),
802 case PLL_CPLL: in rk3328_clk_get_rate()
879 case PLL_CPLL: in rk3328_clk_set_rate()
1101 else if (parent->id == PLL_CPLL) in rk3328_lcdc_set_parent()
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| H A D | clk_rk1808.c | 60 RK1808_CLK_DUMP(PLL_CPLL, "cpll", true),
84 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK1808_PLL_CON(16),
915 case PLL_CPLL: in rk1808_clk_get_rate()
1008 case PLL_CPLL: in rk1808_clk_set_rate()
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| H A D | clk_rv1106.c | 43 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1106_PLL_CON(8),
63 RV1106_CLK_DUMP(PLL_CPLL, "cpll", true),
1059 case PLL_CPLL: in rv1106_clk_get_rate()
1160 case PLL_CPLL: in rv1106_clk_set_rate()
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| H A D | clk_rk3399.c | 80 RK3399_CLK_DUMP(PLL_CPLL, "cpll", true),
425 case PLL_CPLL: in rk3399_pll_get_rate()
1150 case PLL_CPLL: in rk3399_clk_get_rate()
1344 if (parent->id == PLL_CPLL) { in rk3399_dclk_vop_set_parent()
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| H A D | clk_rk3576.c | 75 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
96 RK3576_CLK_DUMP(PLL_CPLL, "cpll", true),
2082 case PLL_CPLL: in rk3576_clk_get_rate()
2236 case PLL_CPLL: in rk3576_clk_set_rate()
2397 else if (parent->id == PLL_CPLL) in rk3576_dclk_vop_set_parent()
2444 else if (parent->id == PLL_CPLL) in rk3576_dclk_vop_set_parent()
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| H A D | clk_rk3528.c | 69 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
125 RK3528_CLK_DUMP(PLL_CPLL, "cpll"),
1349 case PLL_CPLL: in rk3528_clk_get_rate()
1468 case PLL_CPLL: in rk3528_clk_set_rate()
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| H A D | clk_rv1126b.c | 48 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126B_PERIPLL_CON(0),
63 RV1126B_CLK_DUMP(PLL_CPLL, "cpll", true),
1485 case PLL_CPLL: in rv1126b_clk_get_rate()
1617 case PLL_CPLL: in rv1126b_clk_set_rate()
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| H A D | clk_rk3368.c | 76 RK3368_CLK_DUMP(PLL_CPLL, "cpll", true),
938 case PLL_CPLL: in rk3368_clk_get_rate()
1007 case PLL_CPLL: in rk3368_clk_set_rate()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3568/ |
| H A D | rk3568.c | 1196 pp[3] = cpu_to_fdt32(PLL_CPLL); in rk_board_fdt_fixup()
1197 pp[5] = cpu_to_fdt32(PLL_CPLL); in rk_board_fdt_fixup()
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