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Searched refs:CONFIG_SYS_PCIE1_MEM_PHYS (Results 1 – 25 of 72) sorted by relevance

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/rk3399_rockchip-uboot/board/varisys/cyrus/
H A Dtlb.c60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
66 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
71 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/rk3399_rockchip-uboot/board/freescale/t4rdb/
H A Dtlb.c56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
62 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
67 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/rk3399_rockchip-uboot/board/freescale/t4qds/
H A Dtlb.c69 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
75 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
80 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/rk3399_rockchip-uboot/board/freescale/common/p_corenet/
H A Dtlb.c95 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
101 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
106 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/rk3399_rockchip-uboot/board/gdsys/p1022/
H A Dtlb.c53 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
57 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
/rk3399_rockchip-uboot/board/xes/xpedite537x/
H A Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/xes/xpedite550x/
H A Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/mpc8569mds/
H A Dtlb.c61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
70 (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
/rk3399_rockchip-uboot/include/configs/
H A Dxpedite517x.h289 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
355 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
359 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
363 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
H A Dcontrolcenterd.h230 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
233 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
H A Dsbc8641d.h271 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
362 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
365 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
H A DMPC8548CDS.h361 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull macro
364 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 macro
H A Dcyrus.h257 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
260 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
/rk3399_rockchip-uboot/board/freescale/b4860qds/
H A Dtlb.c67 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
72 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
/rk3399_rockchip-uboot/board/mpc8308_p1m/
H A Dmpc8308_p1m.c31 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/p1_twr/
H A Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/c29xpcie/
H A Dtlb.c39 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/Arcturus/ucp1020/
H A Dtlb.c53 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/p1010rdb/
H A Dtlb.c56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A Dtlb.c61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/keymile/kmp204x/
H A Dtlb.c51 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/t1040qds/
H A Dtlb.c57 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/mpc837xerdb/
H A Dpci.c36 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/t102xqds/
H A Dtlb.c58 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/
H A Dtlb.c49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,

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