1b9944a77SDirk Eibach /* 2b9944a77SDirk Eibach * Copyright 2010 Freescale Semiconductor, Inc. 3b9944a77SDirk Eibach * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4b9944a77SDirk Eibach * Timur Tabi <timur@freescale.com> 5b9944a77SDirk Eibach * 6*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0+ 7b9944a77SDirk Eibach */ 8b9944a77SDirk Eibach 9b9944a77SDirk Eibach #include <common.h> 10b9944a77SDirk Eibach #include <asm/mmu.h> 11b9944a77SDirk Eibach 12b9944a77SDirk Eibach struct fsl_e_tlb_entry tlb_table[] = { 13b9944a77SDirk Eibach /* TLB 0 - for temp stack in cache */ 14b9944a77SDirk Eibach SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 15b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, 0, 16b9944a77SDirk Eibach 0, 0, BOOKE_PAGESZ_4K, 0), 17b9944a77SDirk Eibach SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18b9944a77SDirk Eibach CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, 0, 20b9944a77SDirk Eibach 0, 0, BOOKE_PAGESZ_4K, 0), 21b9944a77SDirk Eibach SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22b9944a77SDirk Eibach CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, 0, 24b9944a77SDirk Eibach 0, 0, BOOKE_PAGESZ_4K, 0), 25b9944a77SDirk Eibach SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 26b9944a77SDirk Eibach CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, 0, 28b9944a77SDirk Eibach 0, 0, BOOKE_PAGESZ_4K, 0), 29b9944a77SDirk Eibach 30b9944a77SDirk Eibach /* TLB 1 */ 31b9944a77SDirk Eibach /* *I*** - Covers boot page */ 32b9944a77SDirk Eibach SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 33b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 34b9944a77SDirk Eibach 0, 0, BOOKE_PAGESZ_4K, 1), 35b9944a77SDirk Eibach 36b9944a77SDirk Eibach /* *I*G* - CCSRBAR */ 37b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 38b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39b9944a77SDirk Eibach 0, 1, BOOKE_PAGESZ_1M, 1), 40b9944a77SDirk Eibach 41b9944a77SDirk Eibach /* *I*G* - eLBC */ 42b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS, 43b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 44b9944a77SDirk Eibach 0, 2, BOOKE_PAGESZ_1M, 1), 45b9944a77SDirk Eibach 46b9944a77SDirk Eibach #if defined(CONFIG_TRAILBLAZER) 47b9944a77SDirk Eibach /* *I*G - L2SRAM */ 48b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 49b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50b9944a77SDirk Eibach 0, 9, BOOKE_PAGESZ_256K, 1), 51b9944a77SDirk Eibach #else 52b9944a77SDirk Eibach /* *I*G* - PCI */ 53b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 54b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55b9944a77SDirk Eibach 0, 3, BOOKE_PAGESZ_256M, 1), 56b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, 57b9944a77SDirk Eibach CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, 58b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59b9944a77SDirk Eibach 0, 4, BOOKE_PAGESZ_256M, 1), 60b9944a77SDirk Eibach 61b9944a77SDirk Eibach /* *I*G* - PCI I/O */ 62b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 63b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64b9944a77SDirk Eibach 0, 5, BOOKE_PAGESZ_256K, 1), 65b9944a77SDirk Eibach 66b9944a77SDirk Eibach #ifdef CONFIG_SYS_RAMBOOT 67b9944a77SDirk Eibach SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 68b9944a77SDirk Eibach MAS3_SX|MAS3_SW|MAS3_SR, 0, 69b9944a77SDirk Eibach 0, 6, BOOKE_PAGESZ_1G, 1), 70b9944a77SDirk Eibach #endif 71b9944a77SDirk Eibach #endif 72b9944a77SDirk Eibach }; 73b9944a77SDirk Eibach 74b9944a77SDirk Eibach int num_tlb_entries = ARRAY_SIZE(tlb_table); 75