149f5befaSXie Xiaobo /* 249f5befaSXie Xiaobo * Copyright 2013 Freescale Semiconductor, Inc. 349f5befaSXie Xiaobo * 4*3aab0cd8SYork Sun * SPDX-License-Identifier: GPL-2.0+ 549f5befaSXie Xiaobo */ 649f5befaSXie Xiaobo 749f5befaSXie Xiaobo #include <common.h> 849f5befaSXie Xiaobo #include <asm/mmu.h> 949f5befaSXie Xiaobo 1049f5befaSXie Xiaobo struct fsl_e_tlb_entry tlb_table[] = { 1149f5befaSXie Xiaobo /* TLB 0 - for temp stack in cache */ 1249f5befaSXie Xiaobo SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 1349f5befaSXie Xiaobo CONFIG_SYS_INIT_RAM_ADDR_PHYS, 1449f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, 0, 1549f5befaSXie Xiaobo 0, 0, BOOKE_PAGESZ_4K, 0), 1649f5befaSXie Xiaobo SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 1749f5befaSXie Xiaobo CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 1849f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, 0, 1949f5befaSXie Xiaobo 0, 0, BOOKE_PAGESZ_4K, 0), 2049f5befaSXie Xiaobo SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 2149f5befaSXie Xiaobo CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 2249f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, 0, 2349f5befaSXie Xiaobo 0, 0, BOOKE_PAGESZ_4K, 0), 2449f5befaSXie Xiaobo SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 2549f5befaSXie Xiaobo CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 2649f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, 0, 2749f5befaSXie Xiaobo 0, 0, BOOKE_PAGESZ_4K, 0), 2849f5befaSXie Xiaobo 2949f5befaSXie Xiaobo /* TLB 1 */ 3049f5befaSXie Xiaobo /* *I*** - Covers boot page */ 3149f5befaSXie Xiaobo SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 3249f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 3349f5befaSXie Xiaobo 0, 0, BOOKE_PAGESZ_4K, 1), 3449f5befaSXie Xiaobo 3549f5befaSXie Xiaobo /* *I*G* - CCSRBAR */ 3649f5befaSXie Xiaobo SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 3749f5befaSXie Xiaobo MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 3849f5befaSXie Xiaobo 0, 1, BOOKE_PAGESZ_1M, 1), 3949f5befaSXie Xiaobo 4049f5befaSXie Xiaobo #ifndef CONFIG_SPL_BUILD 4149f5befaSXie Xiaobo /* W**G* - Flash, localbus */ 4249f5befaSXie Xiaobo /* This will be changed to *I*G* after relocation to RAM. */ 4349f5befaSXie Xiaobo SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 4449f5befaSXie Xiaobo MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 4549f5befaSXie Xiaobo 0, 2, BOOKE_PAGESZ_64M, 1), 4649f5befaSXie Xiaobo 4749f5befaSXie Xiaobo /* W**G* - Flash, localbus */ 4849f5befaSXie Xiaobo /* This will be changed to *I*G* after relocation to RAM. */ 4949f5befaSXie Xiaobo SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, 5049f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 5149f5befaSXie Xiaobo 0, 5, BOOKE_PAGESZ_1M, 1), 5249f5befaSXie Xiaobo 5349f5befaSXie Xiaobo #ifdef CONFIG_PCI 5449f5befaSXie Xiaobo /* *I*G* - PCI memory 1.5G */ 5549f5befaSXie Xiaobo SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 5649f5befaSXie Xiaobo MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 5749f5befaSXie Xiaobo 0, 3, BOOKE_PAGESZ_1G, 1), 5849f5befaSXie Xiaobo 5949f5befaSXie Xiaobo /* *I*G* - PCI I/O effective: 192K */ 6049f5befaSXie Xiaobo SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 6149f5befaSXie Xiaobo MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6249f5befaSXie Xiaobo 0, 4, BOOKE_PAGESZ_256K, 1), 6349f5befaSXie Xiaobo #endif 6449f5befaSXie Xiaobo 6549f5befaSXie Xiaobo #endif 6649f5befaSXie Xiaobo 6749f5befaSXie Xiaobo #ifdef CONFIG_SYS_RAMBOOT 6849f5befaSXie Xiaobo /* *I*G - eSDHC boot */ 6949f5befaSXie Xiaobo SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 7049f5befaSXie Xiaobo MAS3_SX|MAS3_SW|MAS3_SR, 0, 7149f5befaSXie Xiaobo 0, 8, BOOKE_PAGESZ_1G, 1), 7249f5befaSXie Xiaobo #endif 7349f5befaSXie Xiaobo 7449f5befaSXie Xiaobo }; 7549f5befaSXie Xiaobo 7649f5befaSXie Xiaobo int num_tlb_entries = ARRAY_SIZE(tlb_table); 77