141d91011SPrabhakar Kushwaha /* 241d91011SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 341d91011SPrabhakar Kushwaha * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 541d91011SPrabhakar Kushwaha */ 641d91011SPrabhakar Kushwaha 741d91011SPrabhakar Kushwaha #include <common.h> 841d91011SPrabhakar Kushwaha #include <asm/mmu.h> 941d91011SPrabhakar Kushwaha 1041d91011SPrabhakar Kushwaha struct fsl_e_tlb_entry tlb_table[] = { 1141d91011SPrabhakar Kushwaha /* TLB 0 - for temp stack in cache */ 1241d91011SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 1341d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 1441d91011SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 1541d91011SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 1641d91011SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 1741d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 1841d91011SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 1941d91011SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 2041d91011SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 2141d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 2241d91011SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 2341d91011SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 2441d91011SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 2541d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 2641d91011SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 2741d91011SPrabhakar Kushwaha 2841d91011SPrabhakar Kushwaha /* TLB 1 */ 2941d91011SPrabhakar Kushwaha /* *I*** - Covers boot page */ 30f64bd7c0SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31f64bd7c0SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 32f64bd7c0SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 1), 33*fbe76ae4SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 3483e0c2bbSPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 3541d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36f64bd7c0SPrabhakar Kushwaha 0, 10, BOOKE_PAGESZ_4K, 1), 37f64bd7c0SPrabhakar Kushwaha #endif 3841d91011SPrabhakar Kushwaha 3941d91011SPrabhakar Kushwaha /* *I*G* - CCSRBAR (PA) */ 4041d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 4141d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 4241d91011SPrabhakar Kushwaha 0, 1, BOOKE_PAGESZ_1M, 1), 4341d91011SPrabhakar Kushwaha 4464501c66SPriyanka Jain /* CCSRBAR (DSP) */ 4564501c66SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 4664501c66SPriyanka Jain CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, 4764501c66SPriyanka Jain MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), 4864501c66SPriyanka Jain 4983e0c2bbSPrabhakar Kushwaha #ifndef CONFIG_SPL_BUILD 5041d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 5141d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 5241d91011SPrabhakar Kushwaha 0, 3, BOOKE_PAGESZ_64M, 1), 5341d91011SPrabhakar Kushwaha 5441d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, 5541d91011SPrabhakar Kushwaha CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 5641d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 5741d91011SPrabhakar Kushwaha 0, 4, BOOKE_PAGESZ_64M, 1), 5841d91011SPrabhakar Kushwaha 5941d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 6041d91011SPrabhakar Kushwaha /* *I*G* - PCI */ 6141d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 6241d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6341d91011SPrabhakar Kushwaha 0, 6, BOOKE_PAGESZ_256M, 1), 6441d91011SPrabhakar Kushwaha 6541d91011SPrabhakar Kushwaha /* *I*G* - PCI I/O */ 6641d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 6741d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6841d91011SPrabhakar Kushwaha 0, 7, BOOKE_PAGESZ_64K, 1), 6941d91011SPrabhakar Kushwaha #endif 7083e0c2bbSPrabhakar Kushwaha #endif 7141d91011SPrabhakar Kushwaha 7283e0c2bbSPrabhakar Kushwaha #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 7383e0c2bbSPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 7483e0c2bbSPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 7583e0c2bbSPrabhakar Kushwaha 0, 8, BOOKE_PAGESZ_1G, 1), 7683e0c2bbSPrabhakar Kushwaha #endif 7783e0c2bbSPrabhakar Kushwaha 7883e0c2bbSPrabhakar Kushwaha #ifdef CONFIG_SYS_FPGA_BASE 7941d91011SPrabhakar Kushwaha /* *I*G - Board FPGA */ 8041d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, 8141d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 8241d91011SPrabhakar Kushwaha 0, 9, BOOKE_PAGESZ_256K, 1), 8383e0c2bbSPrabhakar Kushwaha #endif 8441d91011SPrabhakar Kushwaha 8583e0c2bbSPrabhakar Kushwaha #ifdef CONFIG_SYS_NAND_BASE_PHYS 8641d91011SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 8741d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 8841d91011SPrabhakar Kushwaha 0, 5, BOOKE_PAGESZ_1M, 1), 8983e0c2bbSPrabhakar Kushwaha #endif 9041d91011SPrabhakar Kushwaha }; 9141d91011SPrabhakar Kushwaha 9241d91011SPrabhakar Kushwaha int num_tlb_entries = ARRAY_SIZE(tlb_table); 93