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Searched refs:write_ctx_reg (Results 1 – 25 of 37) sorted by relevance

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/rk3399_ARM-atf/services/std_svc/spmd/
H A Dspmd_pm.c93 write_ctx_reg(el3_state, CTX_ELR_EL3, entry_point); in spmd_cpu_on_finish_handler()
133 write_ctx_reg(gpregs, CTX_GPREG_X8, 0); in spmd_cpu_off_handler()
134 write_ctx_reg(gpregs, CTX_GPREG_X9, 0); in spmd_cpu_off_handler()
135 write_ctx_reg(gpregs, CTX_GPREG_X10, 0); in spmd_cpu_off_handler()
136 write_ctx_reg(gpregs, CTX_GPREG_X11, 0); in spmd_cpu_off_handler()
137 write_ctx_reg(gpregs, CTX_GPREG_X12, 0); in spmd_cpu_off_handler()
138 write_ctx_reg(gpregs, CTX_GPREG_X13, 0); in spmd_cpu_off_handler()
139 write_ctx_reg(gpregs, CTX_GPREG_X14, 0); in spmd_cpu_off_handler()
140 write_ctx_reg(gpregs, CTX_GPREG_X15, 0); in spmd_cpu_off_handler()
141 write_ctx_reg(gpregs, CTX_GPREG_X16, 0); in spmd_cpu_off_handler()
[all …]
H A Dspmd_logical_sp.c143 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); in spmd_build_direct_message_req()
144 write_ctx_reg(gpregs, CTX_GPREG_X1, x1); in spmd_build_direct_message_req()
145 write_ctx_reg(gpregs, CTX_GPREG_X2, x2); in spmd_build_direct_message_req()
146 write_ctx_reg(gpregs, CTX_GPREG_X3, x3); in spmd_build_direct_message_req()
147 write_ctx_reg(gpregs, CTX_GPREG_X4, x4); in spmd_build_direct_message_req()
148 write_ctx_reg(gpregs, CTX_GPREG_X5, 0U); in spmd_build_direct_message_req()
149 write_ctx_reg(gpregs, CTX_GPREG_X6, 0U); in spmd_build_direct_message_req()
150 write_ctx_reg(gpregs, CTX_GPREG_X7, 0U); in spmd_build_direct_message_req()
199 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_PARTITION_INFO_GET_REGS_SMC64); in spmd_build_ffa_info_get_regs()
200 write_ctx_reg(gpregs, CTX_GPREG_X1, arg1); in spmd_build_ffa_info_get_regs()
[all …]
H A Dspmd_main.c112 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); in spmd_build_spmc_message()
113 write_ctx_reg(gpregs, CTX_GPREG_X1, in spmd_build_spmc_message()
116 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); in spmd_build_spmc_message()
117 write_ctx_reg(gpregs, CTX_GPREG_X3, message); in spmd_build_spmc_message()
120 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); in spmd_build_spmc_message()
121 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); in spmd_build_spmc_message()
122 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); in spmd_build_spmc_message()
123 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); in spmd_build_spmc_message()
196 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); in spmd_setup_context()
268 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_INTERRUPT); in spmd_secure_interrupt_handler()
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dmce.c194 write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL)); in mce_command_handler()
195 write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL)); in mce_command_handler()
196 write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL)); in mce_command_handler()
209 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); in mce_command_handler()
210 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64)); in mce_command_handler()
223 write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret)); in mce_command_handler()
231 write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret)); in mce_command_handler()
232 write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)(ret)); in mce_command_handler()
251 write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ? in mce_command_handler()
253 write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ? in mce_command_handler()
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_sip_calls.c68 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); in plat_sip_handler()
69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
70 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); in plat_sip_handler()
91 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, local_x1); in plat_sip_handler()
/rk3399_ARM-atf/include/arch/aarch64/
H A Dsmccc_helpers.h37 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
41 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \
45 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
49 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \
53 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
57 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
61 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \
65 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \
76 write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v))
103 write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v))
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_fiq_glue.c139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
140 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); in tegra_fiq_get_intr_context()
143 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); in tegra_fiq_get_intr_context()
146 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); in tegra_fiq_get_intr_context()
/rk3399_ARM-atf/lib/extensions/tcr/
H A Dtcr2.c25 write_ctx_reg(state, CTX_SCR_EL3, reg); in tcr2_enable()
41 write_ctx_reg(state, CTX_SCR_EL3, reg); in tcr2_disable()
/rk3399_ARM-atf/lib/el3_runtime/aarch32/
H A Dcontext_mgmt.c106 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); in cm_setup_context()
121 write_ctx_reg(reg_ctx, CTX_SCR, scr); in cm_setup_context()
122 write_ctx_reg(reg_ctx, CTX_LR, ep->pc); in cm_setup_context()
123 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); in cm_setup_context()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/
H A Dplat_sip_calls.c116 write_ctx_reg(get_gpregs_ctx(handle), in plat_sip_handler()
145 write_ctx_reg(get_gpregs_ctx(handle), in plat_sip_handler()
147 write_ctx_reg(get_gpregs_ctx(handle), in plat_sip_handler()
/rk3399_ARM-atf/lib/extensions/trbe/
H A Dtrbe.c50 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in trbe_enable_ns()
68 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in trbe_disable_all()
/rk3399_ARM-atf/lib/extensions/spe/
H A Dspe.c60 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in spe_enable_ns()
75 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in spe_disable_others()
/rk3399_ARM-atf/services/spd/tlkd/
H A Dtlkd_pm.c55 write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_SUSPEND); in cpu_suspend_handler()
91 write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_RESUME); in cpu_resume_handler()
H A Dtlkd_main.c331 write_ctx_reg(gp_regs, CTX_GPREG_X4, (uint32_t)x2); in tlkd_smc_handler()
332 write_ctx_reg(gp_regs, CTX_GPREG_X5, (uint32_t)(x2 >> 32)); in tlkd_smc_handler()
333 write_ctx_reg(gp_regs, CTX_GPREG_X6, (uint32_t)x3); in tlkd_smc_handler()
334 write_ctx_reg(gp_regs, CTX_GPREG_X7, (uint32_t)(x3 >> 32)); in tlkd_smc_handler()
/rk3399_ARM-atf/lib/extensions/sme/
H A Dsme.c28 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_enable()
89 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_disable()
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/
H A Dspmc_pm.c29 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); in spmc_build_pm_message()
30 write_ctx_reg(gpregs, CTX_GPREG_X1, in spmc_build_pm_message()
33 write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_FWK_MSG_BIT | in spmc_build_pm_message()
35 write_ctx_reg(gpregs, CTX_GPREG_X3, message); in spmc_build_pm_message()
/rk3399_ARM-atf/services/std_svc/spm/spm_mm/
H A Dspm_mm_setup.c178 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, in spm_sp_setup()
322 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, in spm_sp_setup()
324 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, in spm_sp_setup()
326 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, in spm_sp_setup()
328 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, in spm_sp_setup()
H A Dspm_mm_main.c183 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); in spm_mm_sp_call()
184 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1, x1); in spm_mm_sp_call()
185 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); in spm_mm_sp_call()
186 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3, x3); in spm_mm_sp_call()
/rk3399_ARM-atf/lib/extensions/fgt/
H A Dfgt2.c25 write_ctx_reg(state, CTX_SCR_EL3, reg); in fgt2_enable()
/rk3399_ARM-atf/lib/extensions/debug/
H A Ddebugv8p9.c26 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in debugv8p9_extended_bp_wp_enable()
/rk3399_ARM-atf/lib/extensions/trf/aarch64/
H A Dtrf.c31 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in trf_enable()
/rk3399_ARM-atf/lib/extensions/brbe/
H A Dbrbe.c27 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); in brbe_enable()
/rk3399_ARM-atf/bl31/
H A Dbl31_traps.c245 write_ctx_reg(state, CTX_SPSR_EL3, new_spsr); in inject_undef64()
268 write_ctx_reg(state, CTX_SPSR_EL3, new_spsr); in inject_undef64()
269 write_ctx_reg(state, CTX_ELR_EL3, elr_el3); in inject_undef64()
/rk3399_ARM-atf/plat/arm/board/fvp/aarch64/
H A Dfvp_ea.c45 write_ctx_reg(el3_ctx, CTX_ELR_EL3, elr_el3); in plat_ea_handler()
/rk3399_ARM-atf/include/lib/el3_runtime/aarch32/
H A Dcontext.h51 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \ macro

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