1*f4303d05SJayanth Dodderi Chidanand /* 2*f4303d05SJayanth Dodderi Chidanand * Copyright (c) 2024, Arm Limited. All rights reserved. 3*f4303d05SJayanth Dodderi Chidanand * 4*f4303d05SJayanth Dodderi Chidanand * SPDX-License-Identifier: BSD-3-Clause 5*f4303d05SJayanth Dodderi Chidanand */ 6*f4303d05SJayanth Dodderi Chidanand 7*f4303d05SJayanth Dodderi Chidanand #include <arch.h> 8*f4303d05SJayanth Dodderi Chidanand #include <arch_features.h> 9*f4303d05SJayanth Dodderi Chidanand #include <arch_helpers.h> 10*f4303d05SJayanth Dodderi Chidanand #include <lib/extensions/tcr2.h> 11*f4303d05SJayanth Dodderi Chidanand tcr2_enable(cpu_context_t * ctx)12*f4303d05SJayanth Dodderi Chidanandvoid tcr2_enable(cpu_context_t *ctx) 13*f4303d05SJayanth Dodderi Chidanand { 14*f4303d05SJayanth Dodderi Chidanand u_register_t reg; 15*f4303d05SJayanth Dodderi Chidanand el3_state_t *state; 16*f4303d05SJayanth Dodderi Chidanand 17*f4303d05SJayanth Dodderi Chidanand state = get_el3state_ctx(ctx); 18*f4303d05SJayanth Dodderi Chidanand 19*f4303d05SJayanth Dodderi Chidanand /* Set the TCR2EN bit in SCR_EL3 to enable access to TCR2_EL1, 20*f4303d05SJayanth Dodderi Chidanand * and TCR2_EL2 registers . 21*f4303d05SJayanth Dodderi Chidanand */ 22*f4303d05SJayanth Dodderi Chidanand 23*f4303d05SJayanth Dodderi Chidanand reg = read_ctx_reg(state, CTX_SCR_EL3); 24*f4303d05SJayanth Dodderi Chidanand reg |= SCR_TCR2EN_BIT; 25*f4303d05SJayanth Dodderi Chidanand write_ctx_reg(state, CTX_SCR_EL3, reg); 26*f4303d05SJayanth Dodderi Chidanand } 27*f4303d05SJayanth Dodderi Chidanand tcr2_disable(cpu_context_t * ctx)28*f4303d05SJayanth Dodderi Chidanandvoid tcr2_disable(cpu_context_t *ctx) 29*f4303d05SJayanth Dodderi Chidanand { 30*f4303d05SJayanth Dodderi Chidanand u_register_t reg; 31*f4303d05SJayanth Dodderi Chidanand el3_state_t *state; 32*f4303d05SJayanth Dodderi Chidanand 33*f4303d05SJayanth Dodderi Chidanand state = get_el3state_ctx(ctx); 34*f4303d05SJayanth Dodderi Chidanand 35*f4303d05SJayanth Dodderi Chidanand /* Clear the TCR2EN bit in SCR_EL3 to disable access to TCR2_EL1, 36*f4303d05SJayanth Dodderi Chidanand * and TCR2_EL2 registers . 37*f4303d05SJayanth Dodderi Chidanand */ 38*f4303d05SJayanth Dodderi Chidanand 39*f4303d05SJayanth Dodderi Chidanand reg = read_ctx_reg(state, CTX_SCR_EL3); 40*f4303d05SJayanth Dodderi Chidanand reg &= ~SCR_TCR2EN_BIT; 41*f4303d05SJayanth Dodderi Chidanand write_ctx_reg(state, CTX_SCR_EL3, reg); 42*f4303d05SJayanth Dodderi Chidanand } 43