Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19

Tf2.0 tegra downstream rebase 1.7.19

Tegra186: sip_calls: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Tegra186: sip_calls: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses[Rule 20.7]

Change-Id: Ibdae1d18d299562ca2b96b2318b914601c9926b1
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Merge pull request #1733 from vwadekar/tf2.0-tegra-downstream-rebase-1.3.19

Tegra downstream rebase 1.3.19

Tegra186: remove support for Quasi System power off (SC8) state

This patch removes support for the SC8 power state as the feature is no
longer required for Tegra186 projects.

Change-Id: I622a5ddcff

Tegra186: remove support for Quasi System power off (SC8) state

This patch removes support for the SC8 power state as the feature is no
longer required for Tegra186 projects.

Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: sip_calls: fix defects flagged by MISRA scan

Main fixes:

* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts

Tegra: sip_calls: fix defects flagged by MISRA scan

Main fixes:

* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]

Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #925 from dp-arm/dp/spdx

Use SPDX license identifiers

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Merge branch 'integration' into tf_issue_461

Merge pull request #902 from vwadekar/tegra186-sip-mce-calls

Tegra186: Support AARCH32/64 encoding for MCE calls

Tegra186: Support AARCH32/64 encoding for MCE calls

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads

Tegra186: Support AARCH32/64 encoding for MCE calls

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads. This patch supports MCE SMC functions ID for
AARCH32 and AARCH64 architectures to support such clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #895 from vwadekar/tegra186-platform-support-v5

Tegra186 platform support v5

Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requi

Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #891 from vwadekar/tegra186-platform-support-v4

Tegra186 platform support v4

Tegra186: Add smc handler for coresight clock gating

This change adds function to invoke for MISC_CCPLEX ARI calls and
the corresponding smc handler. This can be used to enable/disable
Coresight clo

Tegra186: Add smc handler for coresight clock gating

This change adds function to invoke for MISC_CCPLEX ARI calls and
the corresponding smc handler. This can be used to enable/disable
Coresight clock gating.

Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #884 from vwadekar/tegra186-platform-support-v3

Tegra186 platform support v3

Tegra186: delete 'Video Memory Carveout' handling

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common S

Tegra186: delete 'Video Memory Carveout' handling

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.

Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: Uncore Perfmon ARI Programming

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence hand

Tegra186: mce: Uncore Perfmon ARI Programming

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.

To access an uncore perfmon register, CPU software writes the ARI
request registers to specify

* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).

It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.

The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.

Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #875 from vwadekar/tegra186-platform-support-v2

Tegra186 platform support v2

Tegra186: mce: enable LATIC for chip verification

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows som

Tegra186: mce: enable LATIC for chip verification

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
used for various measurements relevant ot particular locations in
Silicon. They are small counters which can be polled to determine
how fast a particular location in the Silicon is.

Original change by Guy Sotomayor <gsotomayor@nvidia.com>

Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #865 from vwadekar/tegra186-platform-support-v1

Tegra186 platform support v1

Tegra186: implement quasi power off (SC8) state

This patch adds support for the SC8 system power off state. This
state keeps the sensor subsystem powered ON while powering down
the remaining parts o

Tegra186: implement quasi power off (SC8) state

This patch adds support for the SC8 system power off state. This
state keeps the sensor subsystem powered ON while powering down
the remaining parts of the SoC. The CPUs and DRAM are powered down
as part of this state entry and perform a cold boot when exiting SC8.

Change-Id: Iba65c661a7fe077a0d696f114bab3b4595e19a0d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: register FIQ interrupt sources

This patch registers all the FIQ interrupt sources during platform
setup. Currently we support AON and TOP watchdog timer interrupts.

Change-Id: Ibccd866f00

Tegra186: register FIQ interrupt sources

This patch registers all the FIQ interrupt sources during platform
setup. Currently we support AON and TOP watchdog timer interrupts.

Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: add Video memory carveout settings

This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to
program new video memory carveout settings from the NS world.

Change-Id: If9ed818fe71e

Tegra186: add Video memory carveout settings

This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to
program new video memory carveout settings from the NS world.

Change-Id: If9ed818fe71e6cb7461f225090105a4d8883b7a2
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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