| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x3.S | 37 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 43 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 59 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 75 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 99 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 105 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(36) 111 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 121 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(1) 127 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(22) 133 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL [all...] |
| H A D | neoverse_n1.S | 68 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 74 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 89 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 95 sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK 101 sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 107 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 113 sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT 119 sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 125 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 146 sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL [all...] |
| H A D | neoverse_n2.S | 72 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 78 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 84 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, BIT(29) 113 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 119 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 126 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 140 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 147 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 174 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 194 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL [all...] |
| H A D | cortex_x4.S | 46 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 55 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 62 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 77 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 102 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 125 sysreg_bit_set CORTEX_X4_CPUACTLR2_EL1, BIT(22) 132 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 144 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 189 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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| H A D | neoverse_v2.S | 57 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 72 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 85 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, NEOVERSE_V2_CPUACTLR_EL1_BIT_36 95 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 101 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, BIT(22) 107 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, BIT(50) 126 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 142 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 181 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 194 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL [all...] |
| H A D | rainier.S | 48 sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13 56 sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2 60 sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT 63 sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT 80 sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK
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| H A D | cortex_x2.S | 38 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(15) 44 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(8) 50 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(43) 87 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_WS_THR_DISABLE_ALL_BITS 106 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 135 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 141 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(44) 148 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 154 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 170 sysreg_bit_set CORTEX_X2_CPUACTLR_EL [all...] |
| H A D | cortex_a57.S | 68 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD 74 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 84 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI 90 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION 104 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB 110 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE 131 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR 137 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH 143 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH 161 sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE [all …]
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| H A D | cortex_a715.S | 34 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(0) 40 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(9) 46 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 52 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 58 sysreg_bit_set CORTEX_A715_CPUACTLR3_EL1, BIT(12) 64 sysreg_bit_set CORTEX_A715_CPUACTLR4_EL1, BIT(13) 70 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 81 sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT 104 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(0) 110 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL 68 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(0) global() label 74 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(32) global() label [all...] |
| H A D | cortex_a78c.S | 28 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 35 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 41 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(8) 91 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(0) 97 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 103 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(40) 109 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 159 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 165 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 171 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL [all...] |
| H A D | cortex_a720.S | 31 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, (BIT(60) | BIT(61)) 37 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 43 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 76 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 121 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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| H A D | cortex_x1.S | 29 sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1) 35 sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2) 41 sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53) 60 sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46) 73 sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK
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| H A D | cortex_a710.S | 38 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(2) 44 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(10) 50 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(10) 56 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(27) 62 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(15) 68 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(8) 74 sysreg_bit_set CORTEX_A710_CPUACTLR4_EL1, BIT(43) 155 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 161 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 188 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL [all...] |
| H A D | cortex_a55.S | 26 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 32 sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL 33 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 51 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 66 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 72 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 126 sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
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| H A D | cortex_a75.S | 29 sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT 35 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) 68 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 110 sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT 114 sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT 138 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \
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| H A D | neoverse_v1.S | 32 sysreg_bit_set NEOVERSE_V1_CPUACTLR4_EL1, BIT(14) 38 sysreg_bit_set NEOVERSE_V1_CPUACTLR_EL1, BIT(13) 99 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, BIT(8) 105 sysreg_bit_set NEOVERSE_V1_CPUACTLR_EL1, BIT(11) 111 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, BIT(1) 117 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, BIT(12) 124 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 131 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 138 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 145 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL [all...] |
| H A D | cortex_x925.S | 44 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(14) 57 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(42) 84 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 97 sysreg_bit_set CORTEX_X925_CPUACTLR2_EL1, BIT(22) 104 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 116 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 162 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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| H A D | cortex_a76.S | 328 sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION 334 sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_59 368 sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, BIT(11) 374 sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 380 sysreg_bit_set CORTEX_A76_CPUACTLR3_EL1, CORTEX_A76_CPUACTLR3_EL1_BIT_10 386 sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13 392 sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_BIT_51 398 sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13 415 sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2 421 sysreg_bit_set CORTEX_A76_CPUACTLR_EL [all...] |
| H A D | cortex_a78.S | 44 sysreg_bit_set CORTEX_A78_CPUACTLR_EL1, BIT(13) 50 sysreg_bit_set CORTEX_A78_ACTLR5_EL1, BIT(8) 102 sysreg_bit_set CORTEX_A78_CPUACTLR_EL1, BIT(11) 108 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 114 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 120 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(53) 126 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 200 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) 206 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) 229 sysreg_bit_set CORTEX_A78_ACTLR3_EL [all...] |
| H A D | cortex_a78_ae.S | 28 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(53) 34 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, BIT(2) 40 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 98 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0 110 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40 136 sysreg_bit_set CORTEX_A78_AE_CPUACTLR3_EL1, BIT(47) 142 sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, BIT(22) 148 sysreg_bit_set CORTEX_A78_AE_CPUACTLR5_EL1, BIT(50) 167 sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46) 199 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL [all...] |
| H A D | c1_ultra.S | 35 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 52 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR_EL1, BIT(48) 58 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR5_EL1, BIT(13) 64 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR2_EL1, BIT(22) 94 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 106 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41)
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| H A D | c1_premium.S | 35 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 48 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR_EL1, BIT(48) 54 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR5_EL1, BIT(13) 60 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR2_EL1, BIT(22) 91 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 103 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41)
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| H A D | cortex_a77.S | 32 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(0) 33 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(15) 39 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(11) 51 sysreg_bit_set CORTEX_A77_CPUACTLR3_EL1, BIT(10) 57 sysreg_bit_set CORTEX_A77_CPUACTLR_EL1, BIT(13) 102 sysreg_bit_set CORTEX_A77_CPUACTLR_EL1, BIT(11) 108 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 115 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 121 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 158 sysreg_bit_set CORTEX_A77_ACTLR2_EL [all...] |
| H A D | neoverse_v3.S | 54 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 90 sysreg_bit_set NEOVERSE_V3_CPUACTLR2_EL1, BIT(22) 96 sysreg_bit_set NEOVERSE_V3_CPUACTLR4_EL1, BIT(57) 103 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 115 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 154 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
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| H A D | c1_pro.S | 34 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 40 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(42) 52 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(57) 81 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 97 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49)
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