1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a720 27 28.global check_erratum_cortex_a720_3699561 29 30workaround_reset_start cortex_a720, ERRATUM(2729604), ERRATA_A720_2729604 31 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, (BIT(60) | BIT(61)) 32workaround_reset_end cortex_a720, ERRATUM(2729604) 33 34check_erratum_ls cortex_a720, ERRATUM(2729604), CPU_REV(0, 1) 35 36workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 37 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 38workaround_reset_end cortex_a720, ERRATUM(2792132) 39 40check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 41 42workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 43 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 44workaround_reset_end cortex_a720, ERRATUM(2844092) 45 46check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 47 48workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952 49 errata_dsu_2900952_wa_apply 50workaround_reset_end cortex_a720, ERRATUM(2900952) 51 52check_erratum_custom_start cortex_a720, ERRATUM(2900952) 53 check_errata_dsu_2900952_applies 54 ret 55check_erratum_custom_end cortex_a720, ERRATUM(2900952) 56 57workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 58/* Erratum 2926083 workaround is required only if SPE is enabled */ 59#if ENABLE_SPE_FOR_NS != 0 60 /* Check if Static profiling extension is implemented or present. */ 61 mrs x1, id_aa64dfr0_el1 62 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 63 cbz x0, 1f 64 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 65 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 66 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 671: 68#endif 69workaround_reset_end cortex_a720, ERRATUM(2926083) 70 71check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 72 73workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 74 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 75workaround_reset_end cortex_a720, ERRATUM(2940794) 76 77check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 78 79add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561 80 81check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) 82 83workaround_reset_start cortex_a720, ERRATUM(3711910), ERRATA_A720_3711910 84 mov x0, #5 85 msr CORTEX_A720_CPUPSELR_EL3, x0 86 ldr x0, =0xD503329F 87 msr CORTEX_A720_CPUPOR_EL3, x0 88 ldr x0, =0xFFFFF3FF 89 msr CORTEX_A720_CPUPMR_EL3, x0 90 ldr x0, =0x1004003F1 91 msr CORTEX_A720_CPUPCR_EL3, x0 92workaround_reset_end cortex_a720, ERRATUM(3711910) 93 94check_erratum_ls cortex_a720, ERRATUM(3711910), CPU_REV(0, 2) 95 96cpu_reset_func_start cortex_a720 97 /* Disable speculative loads */ 98 msr SSBS, xzr 99 enable_mpmm 100cpu_reset_func_end cortex_a720 101 102 /* ---------------------------------------------------- 103 * HW will do the cache maintenance while powering down 104 * ---------------------------------------------------- 105 */ 106func cortex_a720_core_pwr_dwn 107 /* --------------------------------------------------- 108 * Enable CPU power down bit in power control register 109 * --------------------------------------------------- 110 */ 111 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 112 113 isb 114 ret 115endfunc cortex_a720_core_pwr_dwn 116 117 /* --------------------------------------------- 118 * This function provides Cortex A720-specific 119 * register information for crash reporting. 120 * It needs to return with x6 pointing to 121 * a list of register names in ascii and 122 * x8 - x15 having values of registers to be 123 * reported. 124 * --------------------------------------------- 125 */ 126.section .rodata.cortex_a720_regs, "aS" 127cortex_a720_regs: /* The ascii list of register names to be reported */ 128 .asciz "cpuectlr_el1", "" 129 130func cortex_a720_cpu_reg_dump 131 adr x6, cortex_a720_regs 132 mrs x8, CORTEX_A720_CPUECTLR_EL1 133 ret 134endfunc cortex_a720_cpu_reg_dump 135 136declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 137 cortex_a720_reset_func, \ 138 cortex_a720_core_pwr_dwn 139