12b357c31SManoj Kumar/* 2*89dba82dSBoyan Karatotev * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 32b357c31SManoj Kumar * 42b357c31SManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 52b357c31SManoj Kumar */ 62b357c31SManoj Kumar 72b357c31SManoj Kumar#include <arch.h> 82b357c31SManoj Kumar#include <asm_macros.S> 92b357c31SManoj Kumar#include <context.h> 102b357c31SManoj Kumar#include <cpu_macros.S> 112b357c31SManoj Kumar#include <cpuamu.h> 122b357c31SManoj Kumar#include <rainier.h> 132b357c31SManoj Kumar 142b357c31SManoj Kumar/* Hardware handled coherency */ 152b357c31SManoj Kumar#if HW_ASSISTED_COHERENCY == 0 162b357c31SManoj Kumar#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled" 172b357c31SManoj Kumar#endif 182b357c31SManoj Kumar 192b357c31SManoj Kumar/* 64-bit only core */ 202b357c31SManoj Kumar#if CTX_INCLUDE_AARCH32_REGS == 1 212b357c31SManoj Kumar#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 222b357c31SManoj Kumar#endif 232b357c31SManoj Kumar 24*89dba82dSBoyan Karatotevcpu_reset_prologue rainier 25*89dba82dSBoyan Karatotev 262b357c31SManoj Kumar/* -------------------------------------------------- 272b357c31SManoj Kumar * Disable speculative loads if Rainier supports 282b357c31SManoj Kumar * SSBS. 292b357c31SManoj Kumar * 302b357c31SManoj Kumar * Shall clobber: x0. 312b357c31SManoj Kumar * -------------------------------------------------- 322b357c31SManoj Kumar */ 332b357c31SManoj Kumarfunc rainier_disable_speculative_loads 342b357c31SManoj Kumar /* Check if the PE implements SSBS */ 352b357c31SManoj Kumar mrs x0, id_aa64pfr1_el1 362b357c31SManoj Kumar tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 372b357c31SManoj Kumar b.eq 1f 382b357c31SManoj Kumar 392b357c31SManoj Kumar /* Disable speculative loads */ 402b357c31SManoj Kumar msr SSBS, xzr 412b357c31SManoj Kumar 422b357c31SManoj Kumar1: 432b357c31SManoj Kumar ret 442b357c31SManoj Kumarendfunc rainier_disable_speculative_loads 452b357c31SManoj Kumar 46e8b30c29SMaksims Svecovs /* Rainier R0P0 is based on Neoverse N1 R4P0. */ 47e8b30c29SMaksims Svecovsworkaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343 48e8b30c29SMaksims Svecovs sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13 49e8b30c29SMaksims Svecovsworkaround_reset_end rainier, ERRATUM(1868343) 50a72144fbSManoj Kumar 51e8b30c29SMaksims Svecovscheck_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0) 52a72144fbSManoj Kumar 53e8b30c29SMaksims Svecovscpu_reset_func_start rainier 542b357c31SManoj Kumar bl rainier_disable_speculative_loads 552b357c31SManoj Kumar /* Forces all cacheable atomic instructions to be near */ 56e8b30c29SMaksims Svecovs sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2 57a72144fbSManoj Kumar 58d23acc9eSAndre Przywara#if ENABLE_FEAT_AMU 592b357c31SManoj Kumar /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 60e8b30c29SMaksims Svecovs sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT 612b357c31SManoj Kumar 622b357c31SManoj Kumar /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 63e8b30c29SMaksims Svecovs sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT 642b357c31SManoj Kumar 652b357c31SManoj Kumar /* Enable group0 counters */ 662b357c31SManoj Kumar mov x0, #RAINIER_AMU_GROUP0_MASK 672b357c31SManoj Kumar msr CPUAMCNTENSET_EL0, x0 682b357c31SManoj Kumar#endif 69e8b30c29SMaksims Svecovscpu_reset_func_end rainier 702b357c31SManoj Kumar 712b357c31SManoj Kumar /* --------------------------------------------- 722b357c31SManoj Kumar * HW will do the cache maintenance while powering down 732b357c31SManoj Kumar * --------------------------------------------- 742b357c31SManoj Kumar */ 752b357c31SManoj Kumarfunc rainier_core_pwr_dwn 762b357c31SManoj Kumar /* --------------------------------------------- 772b357c31SManoj Kumar * Enable CPU power down bit in power control register 782b357c31SManoj Kumar * --------------------------------------------- 792b357c31SManoj Kumar */ 80e8b30c29SMaksims Svecovs sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK 812b357c31SManoj Kumar isb 822b357c31SManoj Kumar ret 832b357c31SManoj Kumarendfunc rainier_core_pwr_dwn 842b357c31SManoj Kumar 852b357c31SManoj Kumar /* --------------------------------------------- 862b357c31SManoj Kumar * This function provides Rainier specific 872b357c31SManoj Kumar * register information for crash reporting. 882b357c31SManoj Kumar * It needs to return with x6 pointing to 892b357c31SManoj Kumar * a list of register names in ascii and 902b357c31SManoj Kumar * x8 - x15 having values of registers to be 912b357c31SManoj Kumar * reported. 922b357c31SManoj Kumar * --------------------------------------------- 932b357c31SManoj Kumar */ 942b357c31SManoj Kumar.section .rodata.rainier_regs, "aS" 952b357c31SManoj Kumarrainier_regs: /* The ascii list of register names to be reported */ 962b357c31SManoj Kumar .asciz "cpuectlr_el1", "" 972b357c31SManoj Kumar 982b357c31SManoj Kumarfunc rainier_cpu_reg_dump 992b357c31SManoj Kumar adr x6, rainier_regs 1002b357c31SManoj Kumar mrs x8, RAINIER_CPUECTLR_EL1 1012b357c31SManoj Kumar ret 1022b357c31SManoj Kumarendfunc rainier_cpu_reg_dump 1032b357c31SManoj Kumar 104041d7c7bSManoj Kumardeclare_cpu_ops rainier, RAINIER_MIDR, \ 1052b357c31SManoj Kumar rainier_reset_func, \ 1062b357c31SManoj Kumar rainier_core_pwr_dwn 107